MicroBlaze Processor Reference Guide www.xilinx.com 89
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
bne
Branch if Not Equal
Description
Branch ifrA not equal to 0, tothe instructionlocated in the offsetvalue ofrB. The target of
the branch will be the instruction at address PC + rB.
The mnemonic bned will set the D bit. The D bit determines whether there is a branch
delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction
following thebranch (i.e.in the branch delay slot) is allowed tocomplete executionbefore
executingthe targetinstruction.If the Dbit isnot set, itmeans that thereis no delayslot, so
the instruction to be executed after the branch is the target instruction.
Pseudocode
If rA 0 then
PC
PC + rB
else
PC
PC + 4
if D = 1 then
allow following instruction to complete execution
Registers Altered
PC
Latency
1 cycle (if branch is not taken)
2 cycles (if branch is taken and the D bit is set)
3 cycles (if branch is taken and the D bit is not set)
Note
A delay slot must not be used by the following: IMM, branch, or break instructions. This
also applies to instructions causing recoverable exceptions (e.g. unalignement), when
hardware exceptions are enabled. Interrupts and external hardware breaks are deferred
until after the delay slot branch has been completed.
bne rA, rB Branch if Not Equal
bned rA, rB Branch if Not Equal with Delay
1 0 0 1 1 1 D 0 0 0 1 rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21 31