90 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 4: MicroBlaze Instruction Set Architecture
Branch Immediate if Not Equal
Branch if rA not equal to 0,to theinstruction located in the offset value of IMM. The target
of the branch will be the instruction at address PC + IMM.
The mnemonic bneid will set the D bit. The D bit determines whether there is a branch
delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction
following thebranch (i.e.in the branch delay slot) is allowed tocomplete executionbefore
executingthe targetinstruction.If the Dbit isnot set, itmeans that thereis no delayslot, so
the instruction to be executed after the branch is the target instruction.
If rA 0 then
PC + sext(IMM)
PC + 4
if D = 1 then
allow following instruction to complete execution
Registers Altered
1 cycle (if branch is not taken)
2 cycles (if branch is taken and the D bit is set)
3 cycles (if branch is taken and the D bit is not set)
By default, Type BInstructionswill take the16-bit IMM fieldvalue and sign extendit to 32
bits to use as the immediate operand. This behavior can be overridden by preceding the
Type B instruction with an imm instruction. See the imm instruction for details on using
32-bit immediate values.
A delay slot must not be used by the following: IMM, branch, or break instructions. This
also applies to instructions causing recoverable exceptions (e.g. unalignement), when
hardware exceptions are enabled. Interrupts and external hardware breaks are deferred
until after the delay slot branch has been completed.
bnei rA, IMM Branch Immediate if Not Equal
bneid rA, IMM Branch Immediate if Not Equal with Delay
1 0 1 1 1 1 D 0 0 0 1 rA IMM
0 6 11 16 31