MicroBlaze Processor Reference Guide www.xilinx.com 93
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
bri
Unconditional Branch Immediate
Description
Branch to the instruction located at address determined by IMM, sign-extended to 32 bits.
The mnemonics brlid and bralid will set the L bit. If the L bit is set, linking will be
performed. The current value of PC will be stored in rD.
The mnemonicsbrai, braid and bralid willset the A bit.If the A bit isset, it means thatthe
branch is to an absolute value and the target is the value in IMM, otherwise, it is a relative
branch and the target will be PC + IMM.
The mnemonics brid, braid, brlid and bralid will set the D bit. The D bit determines
whether there is a branch delay slot or not. If the D bit is set, it means that there is a delay
slot and the instruction following the branch (i.e. in the branch delay slot) is allowed to
complete execution before executing the target instruction. If the D bit is not set, it means
that there is no delay slot, so the instruction to be executed after the branch is the target
instruction.
Pseudocode
if L = 1 then
(rD)
PC
if A = 1 then
PC
(IMM)
else
PC
PC + (IMM)
if D = 1 then
allow following instruction to complete execution
Registers Altered
rD
PC
Latency
2 cycles (if the D bit is set)
3 cycles (if the D bit is not set)
bri IMM Branch Immediate
brai IMM Branch Absolute Immediate
brid IMM Branch Immediate with Delay
braid IMM Branch Absolute Immediate with Delay
brlid rD, IMM Branch and Link Immediate with Delay
bralid rD, IMM Branch Absolute and Link Immediate with Delay
1 0 1 1 1 0 rD D A L 0 0 IMM
0 6 11 16 31