MicroBlaze Processor Reference Guide www.xilinx.com 95
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
brk
Break
Description
Branch and link to the instruction located at address value in rB. The current value of PC
will be stored in rD. The BIP flag in the MSR will be set.
Pseudocode
(rD) PC
PC (rB)
MSR[BIP] ← 1
Registers Altered
rD
PC
MSR[BIP]
Latency
3 cycles
brk rD, rB
1 0 0 1 1 0 rD 0 1 1 0 0 rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21 31