user manual

96 www.xilinx.com MicroBlaze Processor Reference Guide

1-800-255-7778 UG081 (v6.0) June 1, 2006

Chapter 4: MicroBlaze Instruction Set Architecture

brki

Break Immediate

Description

Branch and link to the instruction located at address value in IMM, sign-extended to 32

bits. The current value of PC will be stored in rD. The BIP ﬂag in the MSR will be set.

Pseudocode

(rD) ← PC

PC ← sext(IMM)

MSR[BIP] ← 1

Registers Altered

• rD

• PC

• MSR[BIP]

Latency

3 cycles

Note

By default, Type BInstructionswill take the16-bit IMM ﬁeldvalue and sign extendit to 32

bits to use as the immediate operand. This behavior can be overridden by preceding the

Type B instruction with an imm instruction. See the imm instruction for details on using

32-bit immediate values.

brki rD, IMM

1 0 1 1 1 0 rD 0 1 1 0 0 IMM

0 6 11 16 31