User's Manual

ManualsBrandsXilinx ManualsComputer HardwareXilinx SP601 Hardware UG518

[Guide Subtitle]

[optional]

UG518 (v1.1) August 19, 2009 [optional]

SP601 Hardware

User Guide

UG518 (v1.1) August 19, 2009

Summary of content (55 pages)

PAGE 1
SP601 Hardware User Guide [Guide Subtitle] [optional] UG518 (v1.
PAGE 2
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.
PAGE 3
Revision History The following table shows the revision history for this document. Date Version 07/15/2009 1.0 Initial Xilinx release. 08/19/2009 1.1 • • • • • UG518 (v1.1) August 19, 2009 Revision Added Appendix C, “VITA 57.1 FMC Connections.” Updated Figure 1-18 and Figure 1-32. Updated Table 1-4, Table 1-17, and Table 1-20. Added introductory paragraph to Appendix D, “SP601 Master UCF.” Miscellaneous typographical edits and new user guide template. www.xilinx.
PAGE 4
SP601 Hardware User Guide www.xilinx.com UG518 (v1.
PAGE 5
Table of Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typographical . . . . . . . . . . . . . . . . .
PAGE 6
Appendix A: References Appendix B: Default Jumper and Switch Settings Appendix C: VITA 57.1 FMC Connections Appendix D: SP601 Master UCF 6 www.xilinx.com SP601 Hardware User Guide UG518 (v1.
PAGE 7
Preface About This Guide This manual accompanies the Spartan®-6 FPGA SP601 Evaluation Board and contains information about the SP601 hardware and software tools. Guide Contents This manual contains the following chapters: • Chapter 1, “SP601 Evaluation Board,” provides an overview of the embedded development board and details the components and features of the SP601 board. • Appendix A, “References.” • Appendix B, “Default Jumper and Switch Settings.” • Appendix D, “SP601 Master UCF.
PAGE 8
Preface: About This Guide Convention Meaning or Use Example Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the User Guide for more information. Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. Dark Shading Items that are not supported or reserved This feature is not supported Square brackets An optional entry or parameter.
PAGE 9
Chapter 1 SP601 Evaluation Board Overview The SP601 board enables hardware and software developers to create or evaluate designs targeting the Spartan®-6 XC6SLX16-2CSG324 FPGA. The SP601 provides board features for evaluating the Spartan-6 family that are common to most entry-level development environments. Some commonly used features include a DDR2 memory controller, a parallel linear flash, a tri-mode Ethernet PHY, generalpurpose I/O (GPIO), and a UART.
PAGE 10
Chapter 1: SP601 Evaluation Board Features The SP601 board provides the following features: • 1. Spartan-6 XC6SLX16-2CSG324 FPGA • 2. 128 MB DDR2 Component Memory • 3. SPI x4 Flash • 4. Linear Flash BPI • 5. 10/100/1000 Tri-Speed Ethernet PHY • 7. IIC Bus • 8Kb NV memory ♦ External access 2-pin header ♦ VITA 57.1 FMC-LPC connector 8. Clock Generation ♦ Oscillator (Differential) ♦ Oscillator Socket (Single-Ended, 2.5V or 3.3V) • SMA Connectors (Differential) • 9. VITA 57.
PAGE 11
Related Xilinx Documents Block Diagram Figure 1-1 shows a high-level block diagram of the SP601 and its peripherals. X-Ref Target - Figure 1-1 LEDs DIP Switch GPIO Header USB JTAG Connector FMC LPC Expansion Connector 10/100/1000 Ethernet GMII DED Bank 0 2.5 V Parallel Flash Spartan-6 DDR2 Bank 3 1.8V XC6SLX16 Bank 1 2.5V U1 Differential Clock Clock Socket SMA Clock Pushbuttons Bank 2 2.
PAGE 12
Chapter 1: SP601 Evaluation Board Detailed Description Figure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document. X-Ref Target - Figure 1-2 14 13 15 9 8 2 1 7 16 11 4 8 3 5 12 10 6 13 Figure 1-2: SP601 Board Photo The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1.
PAGE 13
Detailed Description Table 1-1: SP601 Features (Cont’d) Number Feature Notes Schematic Page 9 VITA 57.
PAGE 14
Chapter 1: SP601 Evaluation Board Table 1-2: I/O Voltage Rail of FPGA Banks (Cont’d) FPGA Bank I/O Voltage Rail 2 2.5V 3 1.8V References See the Xilinx Spartan-6 FPGA documentation for more information at http://www.xilinx.com/support/documentation/spartan-6.htm. 2. 128 MB DDR2 Component Memory There are 128 MB of DDR2 memory available on the SP601 board. A 1-Gb Elpida EDE1116ACBG (84-ball) DDR2 memory component is accessible through Bank 3 of the LX16 device.
PAGE 15
Detailed Description Table 1-5 shows the connections and pin numbers for the DDR2 Component Memory. Table 1-5: DDR2 Component Memory Connections Memory U2 FPGA U1 SP601 Hardware User Guide UG518 (v1.
PAGE 16
Chapter 1: SP601 Evaluation Board Table 1-5: DDR2 Component Memory Connections (Cont’d) Memory U2 FPGA U1 Schematic Netname Pin Number Name F2 DDR2_BA0 L2 BA0 F1 DDR2_BA1 L3 BA1 E1 DDR2_BA2 L1 BA2 E3 DDR2_WE_B K3 WE L5 DDR2_RAS_B K7 RAS K5 DDR2_CAS_B L7 CAS K6 DDR2_ODT K9 ODT G3 DDR2_CLK_P J8 CK G1 DDR2_CLK_N K8 CK H7 DDR2_CKE K2 CKE L4 DDR2_LDQS_P F7 LDQS L3 DDR2_LDQS_N E8 LDQS P2 DDR2_UDQS_P B7 UDQS P1 DDR2_UDQS_N A8 UDQS K3 DDR2_LDM F3 LDM
PAGE 17
Detailed Description Figure 1-4 provides the UCF constraints for the DDR2 SDRAM data pins, including the I/O pin assignment and I/O standard used.
PAGE 18
Chapter 1: SP601 Evaluation Board 3. SPI x4 Flash The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash through a 2.5V bank. The XC6SLX16-2CSG324 is a master device when accessing an external SPI flash memory device.
PAGE 19
Detailed Description X-Ref Target - Figure 1-7 U1 FPGA SPI INTERFACE J12 U17 DIN,DOUT,CCLK SPI X4 FLASH MEMORY SPIX4_CS_B SPI_CS_B WINBOND W25Q64VSFIG 2 ON = SPI X4 U17 OFF = SPI EXT.
PAGE 20
Chapter 1: SP601 Evaluation Board Figure 1-8 provides the UCF constraints for the SPI serial flash PROM. X-Ref Target - Figure 1-8 NET NET NET NET NET NET "FPGA_D2_MISO3" "SPI_CS_B" "FPGA_D0_DIN_MISO_MISO1" "FPGA_D1_MISO2" "FPGA_MOSI_CSI_B_MISO0" "FPGA_CCLK" Figure 1-8: LOC LOC LOC LOC LOC LOC = = = = = = "V14"; "V3"; "R13"; "T14"; "T13"; "R15"; UCF Location Constraints for BPI Flash Connections References See the Winbond Serial Flash specifications for more information at http://www.winbondusa.
PAGE 21
Detailed Description Table 1-7: BPI Memory Connections (Cont’d) BPI Memory U10 FPGA U1 Pin SP601 Hardware User Guide UG518 (v1.
PAGE 22
Chapter 1: SP601 Evaluation Board Table 1-7: BPI Memory Connections (Cont’d) BPI Memory U10 FPGA U1 Pin Schematic Netname Pin Number Pin L17 FLASH_CE_B 14 CE0 B3 FMC_PWR_GOOD_FLASH_RST_B 16 RP_B Note: Memory U10 pin 56 address A24 is not connected on the 16 MB device. It is made available for larger density devices.
PAGE 23
Detailed Description 5. 10/100/1000 Tri-Speed Ethernet PHY The SP601 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports a GMII/MII interface from the FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector with built-in magnetics. On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in Table 1-8.
PAGE 24
Chapter 1: SP601 Evaluation Board Table 1-9: FPGA U1 Pin PHY Connections (Cont’d) Schematic Netname P18 PHY_RXD7 120 A9 PHY_TXC_GTXCLK 14 B9 PHY_TXCLK 10 A8 PHY_TXER 13 B8 PHY_TXCTL_TXEN 16 F8 PHY_TXD0 18 G8 PHY_TXD1 19 A6 PHY_TXD2 20 B6 PHY_TXD3 24 E6 PHY_TXD4 25 F7 PHY_TXD5 26 A5 PHY_TXD6 28 C5 PHY_TXD7 29 X-Ref Target - Figure 1-11 NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "PHY_COL" "PHY_
PAGE 25
Detailed Description References See the Marvell Alaska Gigabit Ethernet Transceiver product page for more information at http://www.marvell.com/products/transceivers/alaska_gigabit/index.jsp. Also, see the Xilinx Tri-Mode Ethernet MAC User Guide at http://www.xilinx.com/support/documentation/ip_documentation/tri_mode_eth_ma c_ug138.pdf. 6. USB-to-UART Bridge The SP601 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which allows connection to a host computer with a USB cable.
PAGE 26
Chapter 1: SP601 Evaluation Board References Technical information on the Silicon Labs CP2103GM and the VCP drivers can be found on their website at https://www.silabs.com/Pages/default.aspx. In addition, see some of the Xilinx UART IP specifications at: • • • http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf http://www.xilinx.com/support/documentation/ip_documentation/xps_uartlite.pdf http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdf 7.
PAGE 27
Detailed Description 8-Kb NV Memory The SP601 hosts a 8-Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage memory device (U7). The IIC address of U7 is 0b1010100, and U7 is not write protected (WP pin 7 is tied to GND).
PAGE 28
Chapter 1: SP601 Evaluation Board Oscillator Socket (Single-Ended, 2.5V or 3.3V) One populated single-ended clock socket (X2) is provided for user applications. The option of 3.3V or 2.5V power may be selected via a 0 ohm resistor selection. The SP601 board is shipped with a 27MHz 2.5V oscillator installed.
PAGE 29
Detailed Description Table 1-13: LPC Pinout K J H G F E D C B A 1 NC NC VREF_A_M2C GND NC NC PG_C2M GND NC NC 2 NC NC PRSNT_M2C_L CLK1_M2C_P NC NC GND DP0_C2M_P NC NC 3 NC NC GND CLK1_M2C_N NC NC GND DP0_C2M_N NC NC 4 NC NC CLK0_M2C_P GND NC NC GBTCLK0_M2C_P GND NC NC 5 NC NC CLK0_M2C_N GND NC NC GBTCLK0_M2C_N GND NC NC 6 NC NC GND LA00_P_CC NC NC GND DP0_M2C_P NC NC 7 NC NC LA02_P LA00_N_CC NC NC GND DP0_M2C_N NC NC 8
PAGE 30
Chapter 1: SP601 Evaluation Board Table 1-13: LPC Pinout (Cont’d) K J H G F E D C B A 34 NC NC LA30_P LA31_N NC NC TRST_L GA0 NC NC 35 NC NC LA30_N GND NC NC GA1 12P0V NC NC 36 NC NC GND LA33_P NC NC 3P3V GND NC NC 37 NC NC LA32_P LA33_N NC NC GND 12P0V NC NC 38 NC NC LA32_N GND NC NC 3P3V GND NC NC 39 NC NC GND VADJ NC NC GND 3P3V NC NC 40 NC NC VADJ GND NC NC 3P3V GND NC NC 30 www.xilinx.
PAGE 31
Detailed Description X-RefNET Target - Figure 1-18 "FMC_CLK0_M2C_N" NET "FMC_CLK0_M2C_P" NET "FMC_CLK1_M2C_N" NET "FMC_CLK1_M2C_P" NET "FMC_LA00_CC_N" NET "FMC_LA00_CC_P" NET "FMC_LA01_CC_N" NET "FMC_LA01_CC_P" NET "FMC_LA02_N" NET "FMC_LA02_P" NET "FMC_LA03_N" NET "FMC_LA03_P" NET "FMC_LA04_N" NET "FMC_LA04_P" NET "FMC_LA05_N" NET "FMC_LA05_P" NET "FMC_LA06_N" NET "FMC_LA06_P" NET "FMC_LA07_N" NET "FMC_LA07_P" NET "FMC_LA08_N" NET "FMC_LA08_P" NET "FMC_LA09_N" NET "FMC_LA09_P" NET "FMC_LA10_N" NET "FMC_LA
PAGE 32
Chapter 1: SP601 Evaluation Board 10. Status LEDs Table 1-14 defines the status LEDs.
PAGE 33
Detailed Description 11. FPGA Awake LED and Suspend Jumper The suspend mode jumper permits the FPGA to enter an inactive, "suspend" mode. The FPGA Awake LED DS8 will go out when the FPGA enters this mode. X-Ref Target - Figure 1-19 FPGA AWAKE 2 VCC2V5 DS8 LED-GRN-SMT FPGA SUSPEND 1 1 2 J14 2 OFF = AWAKE (default) ON = SUSPEND 1 R88 27.4 1% 1/16W 2 1 R18 4.
PAGE 34
Chapter 1: SP601 Evaluation Board 12. FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and configuration status LEDs are present on the SP601. The INIT LED DS10 comes on after the FPGA powers up and completes its internal power-on process. The DONE LED DS9 comes on after the FPGA programming bitstream has been downloaded and the FPGA successfully configured. X-Ref Target - Figure 1-21 VCC2V5 1 R113 332 1% 1/16W VCC2V5 2 FPGA DONE 2 2 2 FPGA INIT B R90 27.
PAGE 35
Detailed Description 13. User I/O The SP601 provides the following user and general purpose I/O capabilities: • User LEDs • User DIP switch • Pushbutton switches • CPU Reset pushbutton switch • GPIO male pin header Note: All GPIO location constraints are collected in one partial UCF in Figure 1-27. User LEDs The SP601 provides four active high, green LEDs, as described in Figure 1-23 and Table 1-17. X-Ref Target - Figure 1-23 GPIO LED 3 GPIO LED 2 GPIO LED 1 GPIO LED 0 2 2 1 R93 27.
PAGE 36
Chapter 1: SP601 Evaluation Board Table 1-17: User LEDs (Cont’d) Reference Designator Signal Name Color DS13 GPIO_LED_2 Green C4 DS14 GPIO_LED_3 Green A4 Label FPGA Pin User DIP switch The SP601 includes an active high four pole DIP switch, as described in Figure 1-24 and Table 1-18. X-Ref Target - Figure 1-24 VCC2V5 GPIO_SWITCH_0 GPIO_SWITCH_1 GPIO_SWITCH_2 GPIO_SWITCH_3 1 8 2 7 3 6 4 5 SW8 SDMX-4-X 1 2 1 R22 4.7K 5% 1/16W 2 R21 4.7K 5% 1/16W 1 2 R20 4.
PAGE 37
Detailed Description User Pushbutton Switches The SP601 provides five active high pushbutton switches: SW6, SW4, SW5, SW7 and SW9. The five pushbuttons all have the same topology as the sample shown in Figure 1-25. Four pushbuttons are assigned as GPIO, and the fifth is assigned as a CPU_RESET. Figure 1-25 and Table 1-19 describe the pushbutton switches. X-Ref Target - Figure 1-25 VCC1V8 Pushbutton 1 2 CPU_RESET P1 P4 P2 P3 4 3 SW9 1 R188 2 4.
PAGE 38
Chapter 1: SP601 Evaluation Board GPIO Male Pin Header The SP601 provides a 2X6 GPIO male pin header supporting 3.3V power, GND and eight I/Os. Figure 1-26 and Table 1-20 describe the J13 GPIO Male Pin Header.
PAGE 39
Detailed Description X-Ref Target - Figure 1-27 NET NET NET NET "GPIO_LED_0" "GPIO_LED_1" "GPIO_LED_2" "GPIO_LED_3" LOC LOC LOC LOC = = = = "E13"; "C14"; "C4"; "A4"; NET NET NET NET "GPIO_SWITCH_0" "GPIO_SWITCH_1" "GPIO_SWITCH_2" "GPIO_SWITCH_3" LOC LOC LOC LOC = = = = "D14"; "E12"; "F12"; "V13"; NET NET NET NET NET "GPIO_BUTTON0" "GPIO_BUTTON1" "GPIO_BUTTON2" "GPIO_BUTTON3" "CPU_RESET" LOC LOC LOC LOC LOC = = = = = "P4"; "F6"; "E4"; "F5"; "N4"; NET NET NET NET NET NET NET NET "GPIO_HDR0"
PAGE 40
Chapter 1: SP601 Evaluation Board 14. FPGA_PROG_B Pushbutton Switch The SP601 provides one dedicated, active low FPGA_PROG_B pushbutton switch, as shown in Figure 1-28. X-Ref Target - Figure 1-28 VCC2V5 1 2 R24 4.
PAGE 41
Power Management The SP601 uses power solutions from LTC. An estimate of the current draw on the various power supply rails is shown in Table 1-22. X-Ref Target - Figure 1-30 5V PWR Jack Monolithic Regulator 0.9V@3A max Dual Switcher LTM4616 3. 3V@8A max 2. 5V@8A max Dual Switcher LTM4616 1. 2V@8A max 1. 8V@8A max Linear Regulator LT1763 3.
PAGE 42
Chapter 1: SP601 Evaluation Board Configuration Options The FPGA on the SP601 Evaluation Board can be configured by the following methods: • “3. SPI x4 Flash,” page 18 • “4. Linear Flash BPI,” page 20 • “JTAG Configuration,” page 42 For more information, refer to the Spartan-6 FPGA Configuration User Guide.
PAGE 43
Configuration Options X-Ref Target - Figure 1-32 J4 1 FPGA_TD0 Bypass FMC LPC J1 = Jumper 1-2 2 JTAG_TD0 Include FMC LPC J1 = Jumper 2-3 3 FMC_TD0 H - 1x3 UG518_32_081909 Figure 1-32: VITA 57.1 FMC JTAG Bypass Jumper The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software debug.
PAGE 44
Chapter 1: SP601 Evaluation Board 44 www.xilinx.com SP601 Hardware User Guide UG518 (v1.
PAGE 45
Appendix A References This section provides references to documentation supporting Spartan-6 FPGAs, tools, and IP. For additional information, see www.xilinx.com/support/documentation/index.htm. Documents supporting the SP601 Evaluation Board: 1. UG138, LogiCORE™ IP Tri-Mode Ethernet MAC v4.2 User Guide 2. UG380, Spartan-6 FPGA Configuration User Guide 3. UG381, Spartan-6 FPGA SelectIO Resources User Guide 4. UG388, Spartan-6 FPGA Memory Controller User Guide 5. DS614, Clock Generator (v3.
PAGE 46
Appendix A: References 46 www.xilinx.com SP601 Hardware User Guide UG518 (v1.
PAGE 47
Appendix B Default Jumper and Switch Settings Table B-1 shows the default jumper and switch settings for the SP601. Table B-1: Default Jumper and Switch Settings REFDES SW1 SLIDE, POWER ON-OFF SW2 DIP, 2-POLE, MODE Default OFF 1 M0 ON (1) 2 M1 OFF (0) SW8 DIP, 4-POLE, GPIO 1 OFF 2 OFF 3 OFF 4 OFF J4 SP601 Hardware User Guide UG518 (v1.
PAGE 48
Appendix B: Default Jumper and Switch Settings 48 www.xilinx.com SP601 Hardware User Guide UG518 (v1.
PAGE 49
Appendix C VITA 57.1 FMC Connections Table C-1 shows the VITA 57.1 FMC LPC connections. Table C-1: VITA 57.
PAGE 50
Appendix C: VITA 57.1 FMC Connections Table C-1: VITA 57.
PAGE 51
Appendix D SP601 Master UCF The UCF template is provided for designs that target the SP601. Net names provided in the constraints below correlate with net names on the SP601 rev. C schematic. On identifying the appropriate pins, the net names below should be replaced with net names in the user RTL. See the Constraints Guide for more information.
PAGE 52
Appendix D: SP601 Master UCF NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET 52 "DDR2_LDQS_P" "DDR2_ODT" "DDR2_RAS_B" "DDR2_UDM" "DDR2_UDQS_N" "DDR2_UDQS_P" "DDR2_WE_B" "FLASH_A0" "FLASH_A1" "FLASH_A2" "FLASH_A3" "FLASH_A4" "FLASH_A5" "FLASH_A6" "FLASH_A7" "FLASH_A8" "FLASH_A9" "FLASH_A10" "FLASH_A11" "FLASH_A12" "FLASH
PAGE 53
NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET SP601 Hardware User Guide UG518 (v1.
PAGE 54
Appendix D: SP601 Master UCF NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET 54 "FPGA_CMP_MOSI" "FPGA_D0_DIN_MISO_MISO1" "FPGA_D1_MISO2" "FPGA_D2_MISO3" "FPGA_DONE" "FPGA_HSWAPEN" "FPGA_INIT_B" "FPGA_M0_CMP_MISO" "FPGA_M1" "FPGA_MOSI_CSI_B_MISO0" "FPGA_ONCHIP_TERM1" "FPGA_ONCHIP_TERM2" "FPGA_PROG_B" "FPGA_SUSPEND" "FPGA
PAGE 55
NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET SP601 Hardware User Guide UG518 (v1.1) August 19, 2009 "PHY_TXCTL_TXEN" "PHY_TXC_GTXCLK" "PHY_TXD0" "PHY_TXD1" "PHY_TXD2" "PHY_TXD3" "PHY_TXD4" "PHY_TXD5" "PHY_TXD6" "PHY_TXD7" "PHY_TXER" "SMACLK_N" "SMACLK_P" "SPI_CS_B" "SYSCLK_N" "SYSCLK_P" "USB_1_CTS" "USB_1_RTS" "USB_1_RX" "USB_1_TX" "USER_CLOCK" www.xilinx.