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PowerPC™ 405 Processor

Block Reference Guide

Embedded Development Kit

UG018 (v2.0) August 20, 2004

Summary of content (236 pages)

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PowerPC™ 405 Processor Block Reference Guide Embedded Development Kit UG018 (v2.
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R "Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc. The shadow X shown above is a trademark of Xilinx, Inc. ACE Controller, ACE Flash, A.K.A.
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PowerPC™ 405 Processor Block Reference Guide UG018 (v2.0) August 20, 2004 The following table shows the revision history for this document. Version Revision 09/16/02 1.0 Initial Embedded Development Kit (EDK) release. 09/02/03 1.1 Updated for EDK 6.1 release 04/26/04 DRAFT Early Access release (DRAFT). 06/15/04 DRAFT Second Early Access release (DRAFT). 08/20/04 2.0 Updated to include Virtex-4 functionality. UG018 (v2.0) August 20, 2004 www.xilinx.
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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 1-800-255-7778 UG018 (v2.
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Table of Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typographical . . . . . . . . . . . . . . . . . .
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R Instruction-Side PLB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction-Side PLB I/O Signal Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction-Side PLB Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . Instruction-Side PLB Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 50 51 59 Data-Side Processor Local Bus Interface . . . .
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R ISOCM Controller Instruction Fetch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 DSOCM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 ISOCM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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R FCM Store Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 FCM Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 FCM Decoding Using Decode Busy Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Appendix A: RISCWatch and RISCTrace Interfaces RISCWatch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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R Preface About This Guide This guide serves as a technical reference describing the hardware interface to the PowerPC® 405 processor block. It contains information on input/output signals, timing relationships between signals, and the mechanisms software can use to control the interface operation. The document is intended for use by FPGA and system hardware designers and by system programmers who need to understand how certain operations affect hardware external to the processor.
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R Preface: About This Guide Additional Resources For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs. Resource Tutorials Description/URL Tutorials covering Xilinx design flows, from design entry to verification and debugging http://support.xilinx.com/support/techsup/tutorials/index.
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R Convention Meaning or Use Example Commands that you select from a menu File o Open Keyboard shortcuts Ctrl+C Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Development System Reference Guide for more information. Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. Square brackets [ ] An optional entry or parameter.
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R Preface: About This Guide General Conventions Table 1-1 lists the general notational conventions used throughout this document. Table 1-1: General Notational Conventions Convention Definition mnemonic Instruction mnemonics are shown in lower-case bold. variable Variable items are shown in italic. ActiveLow An overbar indicates an active-low signal.
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R Table 1-2: PowerPC 405 Registers (Continued) Register Descriptive Name TCR Timer-control register TSR Timer-status register Terms active As applied to signals, this term indicates a signal is in a state that causes an action to occur in the receiving device, or indicates an action occurred in the sending device. An activehigh signal drives a logic 1 when active. An active-low signal drives a logic 0 when active.
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R 14 Preface: About This Guide exception An abnormal event or condition that requires the processor’s attention. They can be caused by instruction execution or an external device. The processor records the occurrence of an exception and they often cause an interrupt to occur. fill buffer A buffer that receives and sends data and instructions between the processor and PLB. It is used when cache misses occur and when access to non-cacheable memory occurs.
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R OEA The PowerPC operating-environment architecture, which defines the memory-management model, supervisor-level registers and instructions, synchronization requirements, the exception model, and the time-base resources as seen by supervisor programs. on chip In system-on-chip implementations, this indicates on the same FPGA chip as the processor core, but external to the processor core. pending As applied to interrupts, this indicates that an exception occurred, but the interrupt is disabled.
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R 16 Preface: About This Guide UISA The PowerPC user instruction-set architecture, which defines the base user-level instruction set, registers, data types, the memory model, the programming model, and the exception model as seen by user programs. user mode The operating mode typically used by application software. Privileged operations are not allowed in user mode, and software can access a restricted set of registers and memory.
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R Chapter 1 Introduction to the PowerPC 405 Processor The PowerPC 405 is a 32-bit implementation of the PowerPC embedded-environment architecture that is derived from the PowerPC architecture. Specifically, the PowerPC 405 is an embedded PowerPC 405D5 (for Virtex-II Pro) or 405F6 (for Virtex-4) processor core.
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R Chapter 1: Introduction to the PowerPC 405 Processor Table 1-1: Three Levels of PowerPC Architecture User Instruction-Set Architecture (UISA) Virtual Environment Architecture (VEA) Operating Environment Architecture (OEA) x Defines the architecture level to which user-level (sometimes referred to as problem state) software should conform x Defines the base user-level instruction set, user-level registers, data types, floatingpoint memory conventions, exception model as seen by user programs, memory m
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R x Special-purpose registers for controlling the use of debug resources, timer resources, interrupts, real-mode storage attributes, memory-management facilities, and other architected processor resources. x A device-control-register address space for managing on-chip peripherals such as memory controllers. x A dual-level interrupt structure and interrupt-control instructions. x Multiple timer resources.
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R Table 1-2: Chapter 1: Introduction to the PowerPC 405 Processor OEA Features of the PowerPC Embedded-Environment Architecture Operating Environment Features Register model x Privileged special-purpose registers (SPRs) and instructions for accessing those registers x Device control registers (DCRs) and instructions for accessing those registers Storage model x x x x Privileged cache-management instructions Storage-attribute controls Address translation and memory protection Privileged TLB-managem
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R PowerPC 405 Software Features The PowerPC 405 processor core is an implementation of the PowerPC embeddedenvironment architecture. The processor provides fixed-point embedded applications with high performance at low power consumption. It is compatible with the PowerPC UISA. Much of the PowerPC 405 VEA and OEA support is also available in implementations of the PowerPC Book-E architecture.
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R Chapter 1: Introduction to the PowerPC 405 Processor i Write-back and write-through support i Programmable load and store cache line allocation i Operand forwarding during cache line fills i Non-blocking during cache line fills and flushes x Support for on-chip memory (OCM) that can provide memory-access performance identical to a cache hit x Flexible memory management: x x i Translation of the 4 GB logical-address space into the physical-address space i Independent control over instruc
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R Real Mode In real mode, programs address physical memory directly. Virtual Mode In virtual mode, programs address virtual memory and virtual-memory addresses are translated by the processor into physical-memory addresses. This allows programs to access much larger address spaces than might be implemented in the system.
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R Chapter 1: Introduction to the PowerPC 405 Processor Privileged Registers User Registers Machine-State Register General-Purpose Registers r0 r1 . . .
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R Special-Purpose Registers The processor contains a number of 32-bit special-purpose registers (SPRs). SPRs provide access to additional processor resources, such as the count register, the link register, debug resources, timers, interrupt registers, and others. Most SPRs are accessed only by privileged software, but a few, such as the count register and link register, are accessed by all software.
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R Chapter 1: Introduction to the PowerPC 405 Processor PLB Master Read Interface Instruction OCM MMU I-Cache Array I-Cache Controller Instruction Shadow-TLB (4-Entry) Instruction-Cache Unit Data-Cache Unit PLB Master Read Interface Data Shadow-TLB (8-Entry) D-Cache Controller PLB Master Write Interface Fetch and Decode Logic 3-Element Fetch Queue Data OCM Timers Timers and Debug Unified TLB (64-Entry) Cache Units D-Cache Array CPU Execute Unit 32x32 GPR ALU Debug Logic MAC External-
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R read ports and two write ports. During the decode stage, data is read out of the GPRs for use by the execute unit. During the write-back stage, results are written to the GPR. The use of five read/write ports on the GPRs allows the processor to execute load/store operations in parallel with ALU and MAC operations. The execute unit supports all 32-bit PowerPC UISA integer instructions in hardware, and is compliant with the PowerPC embedded-environment architecture specification.
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R Chapter 1: Introduction to the PowerPC 405 Processor Software manages the initialization and replacement of TLB entries. The PowerPC 405 includes instructions for managing TLB entries by software running in privileged mode. This capability gives significant control to system software over the implementation of a page replacement strategy.
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R Timer Resources The PowerPC 405 contains a 64-bit time base and three timers. The time base is incremented synchronously using the CPU clock or an external clock source. The three timers are incremented synchronously with the time base. The three timers supported by the PowerPC 405 are: x Programmable Interval Timer x Fixed Interval Timer x Watchdog Timer Programmable Interval Timer The programmable interval timer (PIT) is a 32-bit register that is decremented at the time-base increment frequency.
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R Chapter 1: Introduction to the PowerPC 405 Processor x Device control register interface x Clock and power management interface x JTAG port interface x On-chip interrupt controller interface x On-chip memory controller interface Processor Local Bus The processor local bus (PLB) interface provides a 32-bit address and three 64-bit data buses attached to the instruction-cache and data-cache units.
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R caches and the time associated with performing cache-line fills and flushes. Unless stated otherwise, the number of cycles described applies to systems having zero-wait-state memory access.
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R 32 Chapter 1: Introduction to the PowerPC 405 Processor www.xilinx.com 1-800-255-7778 PowerPC™ 405 Processor Block Reference Guide UG018 (v2.
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R Chapter 2 Input/Output Interfaces This chapter describes all PowerPC 405 input/output signals associated with the following processor block interfaces: x “Clock and Power Management Interface” x “CPU Control Interface” x “Reset Interface” x “Instruction-Side Processor Local Bus Interface” x “Data-Side Processor Local Bus Interface” x “Device-Control Register Interfaces” x “Internal Device Control Register (DCR) Interface” x “External DCR Bus Interface” x “External Interrupt Controller
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R Chapter 2: Input/Output Interfaces Appendix B, “Signal Summary,” alphabetically lists the signals described in this chapter. The l/O designation and a description summary are included for each signal. Signal Naming Conventions The following convention is used for signal names throughout this document: PREFIX1PREFIX2SIGNAME1[SIGNAME2][NEG][(m:n)] The components of a signal name are as follows: x PREFIX1 is an uppercase prefix identifying the source of the signal.
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R Table 2-1: Signal Name Prefix Definitions (Continued) Prefix1 or Prefix2 Definition Location BRAM BlockSelect RAM Outside XXX Unspecified FPGA unit Outside a. Not to be confused with the OCM controllers, which are located inside the processor block. Clock and Power Management Interface The clock and power management (CPM) interface enables power-sensitive applications to control the processor clock using external logic. The OCM controllers are clocked separately from the processor core.
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R Chapter 2: Input/Output Interfaces i The DBGC405DEBUGHALT chip-input signal (if provided) is asserted. Assertion of this signal indicates that an external debug tool wants to control the PowerPC 405 processor. See “DBGC405DEBUGHALT (Input)” for more information. CPM Interface I/O Signal Summary Figure 2-1 shows the block symbol for the CPM interface. The BRAM clocks associated with the data-side and instruction-side OCM are described in chapter Chapter 3, “PowerPC 405 OCM Controller.
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R Table 2-2: CPM Interface I/O Signals (Continued) I/O Type If Unused C405CPMMSREE O No Connect Indicates the value of MSR[EE]. C405CPMMSRCE O No Connect Indicates the value of MSR[CE]. C405CPMTIMERIRQ O No Connect Indicates a timer-interrupt request occurred. C405CPMTIMERRESETREQ O No Connect Indicates a watchdog-timer reset request occurred. C405CPMCORESLEEPREQ O No Connect Indicates the core is requesting to be put into sleep mode.
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R Chapter 2: Input/Output Interfaces CPMC405TIMERTICK (Input) This signal is used to control the update frequency of the PowerPC 405 time base and PIT (the FIT and WDT are timer events triggered by the time base). The time base is incremented and the PIT is decremented every cycle that CPMC405TIMERTICK and CPMC405CLOCK are both active. CPMC405TIMERTICK should be synchronous with CPMC405CLOCK for the timers to operate predictably.
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R C405CPMMSREE, C405CPMMSRCE, and C405CPMTIMERIRQ signals before using them to control the processor clocks. C405CPMTIMERIRQ (Output) When asserted, this signal indicates a timer exception occurred within the PowerPC 405 and an interrupt request is pending to handle the exception. When deasserted, no timerinterrupt request is pending. This signal is the logical OR of interrupt requests from the programmable-interval timer (PIT), the fixed-interval timer (FIT), and the watchdog timer (WDT).
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R Chapter 2: Input/Output Interfaces x PLBCLK, primary PLB I/O Bus clock. x BRAMISOCMCLK, reference clock for the I-Side OCM controller. x BRAMDSOCMCLK, reference clock for the D-Side OCM controller. x CPMFCMCLK, reference clock for the APU controller (Virtex-4 only). x CPMDCRCLK, reference clock for the external DCR bus (Virtex-4 only). The PowerPC405 processor block supports multiple clock domains. Using several DCM and BUFG components are recommended to create and drive the clock domains.
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R clocks for the OCM controllers in the processor block: BRAMDSOCMCLK (data side controller) and BRAMISOCMCLK (instruction side controllers). The data side controller and the instruction side controllers can run at different frequencies, based upon the access time of the BRAM. When the processor block, OCM controller, and BRAMs run at the same clock frequency, the processor is in single-cycle mode. Multi-cycle mode occurs when the processor is running at a higher frequency than the BRAMs.
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R Table 2-3: Chapter 2: Input/Output Interfaces CPU Control Interface I/O Signals (Continued) I/O Type Signal If Unused Function TIEC405DISOPERANDFWD I Required Disables operand forwarding for load instructions. C405XXXMACHINECHECK O No Connect Indicates a machine-check error has been detected by the PowerPC 405. CPU Control Interface I/O Signal Descriptions The following sections describe the operation of the CPU control-interface I/O signals.
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R instructions following the load require the loaded data. Disabling operand forwarding may improve the performance (clock frequency) of the PowerPC 405. C405XXXMACHINECHECK (Output) When asserted, this signal indicates the PowerPC 405 detected an instruction machinecheck error. When deasserted, no error exists. This signal is asserted when the processor attempts to execute an instruction that was transferred to the PowerPC 405 with the PLBC405ICUERR signal asserted.
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R Chapter 2: Input/Output Interfaces JTGC405TRSTNEG signals for at least sixteen clock cycles. FPGA designers cannot modify the processor block power-on reset mechanism. The reset logic is not required to support all three types of reset. However, distinguishing resets by type can make it easier to isolate errors during system debug. For example, a system could reset the core to recover from an external error that affects software operation.
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R Table 2-6: Reset Interface I/O Signals (Continued) Signal I/O If Unused Type Function RSTC405RESETCORE I Required Resets the processor block, including the PowerPC 405 core logic, data cache, instruction cache, and interface controllers. RSTC405RESETCHIP I Required Indicates a chip-reset occurred. RSTC405RESETSYS I Required Indicates a system-reset occurred. Resets the logic in the PowerPC 405 JTAG unit. JTGC405TRSTNEG I Required Performs a JTAG test reset (TRST).
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R Chapter 2: Input/Output Interfaces RSTC405RESETSYS input to the processor block. When deasserted, no system-reset request exists. Unlike GSR, this output has no associated reset connectivity in the FPGA. The processor asserts this signal when one of the following occurs: x A JTAG debugger sets the reset field in the debug-control register 0 (DBCR0[RST]) to 0b11. x Software sets the reset field in the debug-control register 0 (DBCR0[RST]) to 0b11.
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R Table 2-5, page 44 shows the valid combinations of the RSTC405RESETCORE, RSTC405RESETCHIP, and RSTC405RESETSYS signals and their effect on the DBSR[MRR] field following reset. JTGC405TRSTNEG (Input) This input is the JTAG test reset (TRST) signal. It can be connected to the chip-level TRST signal. Although optional in IEEE Standard 1149.1, this signal is automatically used by the processor block during power-on reset to properly reset all processor block logic, including the JTAG and debug logic.
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R Chapter 2: Input/Output Interfaces x The request priority is indicated by C405PLBICUPRIORITY[0:1]. See “C405PLBICUPRIORITY[0:1] (Output)”. The PLB arbiter uses this information to prioritize simultaneous requests from multiple PLB masters. The processor can abort a PLB fetch request using C405PLBICUABORT. See “C405PLBICUABORT (Output)”. This can occur when a branch instruction is executed or when an interrupt occurs.
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R placed in the ICU fill buffer, but not in the instruction cache. Subsequent instruction fetches from the same non-cacheable line are read from the fill buffer instead of requiring a separate arbitration and transfer sequence across the PLB. Instructions in the fill buffer are fetched with the same performance as a cache hit. The non-cacheable line remains in the fill buffer until the fill buffer is needed by another line transfer.
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R Chapter 2: Input/Output Interfaces x The prefetch address does not fall outside the current 1 KB physical page. Address pipelining of cacheable prefetch requests can occur if all of the following conditions are met: x Address pipelining is supported by the PLB slave. x The ICU is not already involved in an address-pipelined PLB transfer. x A branch or interrupt does not modify the sequential execution of the current (first) instruction-fetch request.
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R Table 2-7: Instruction-Side PLB Interface Signal Summary I/O Type If Unused C405PLBICUREQUEST O No Connect Indicates the ICU is making an instruction-fetch request. C405PLBICUABUS[0:29] O No Connect Specifies the memory address of the instruction-fetch request. Bits 30:31 of the 32-bit address are assumed to be zero. C405PLBICUSIZE[2:3] O No Connect Specifies a four word or eight word line-transfer size.
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R Chapter 2: Input/Output Interfaces C405PLBICUREQUEST (Output) When asserted, this signal indicates the ICU is requesting instructions from a PLB slave device. The PLB slave asserts PLBC405ICUADDRACK to acknowledge the request. The request can be acknowledged in the same cycle it is presented by the ICU. The request is deasserted in the cycle after it is acknowledged by the PLB slave. When deasserted, no unacknowledged instruction-fetch request exists.
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R C405PLBICUSIZE[2:3] (Output) These signals are used to specify the line-transfer size of the instruction-fetch request. A four-word transfer size is specified when C405PLBICUSIZE[2:3] 0b01. An eight-word transfer size is specified when C405PLBICUSIZE[2:3] 0b10. The transfer size is valid in the cycles during which the fetch-request signal (C405PLBICUREQUEST) is asserted.
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R Chapter 2: Input/Output Interfaces C405PLBICUU0ATTR (Output) This signal reflects the value of the user-defined (U0) storage attribute for the target address. The requested instructions are not in memory locations characterized by this attribute when the signal is deasserted (0). They are in memory locations characterized by this attribute when the signal is asserted (1). This signal is valid during the time the fetchrequest signal (C405PLBICUREQUEST) is asserted.
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R PLBC405ICUADDRACK (Input) When asserted, this signal indicates the PLB slave acknowledges the ICU fetch request (indicated by the ICU assertion of C405PLBICUREQUEST). When deasserted, no such acknowledgement exists. A fetch request can be acknowledged by the PLB slave in the same cycle the request is asserted by the ICU.
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R Chapter 2: Input/Output Interfaces x When a 64-bit PLB slave responds, an aligned doubleword is sent from the slave to the ICU during each transfer cycle. Both words are read from the 64-bit interface by the ICU in this cycle. Table 2-10, page 58, shows the location of instructions on the ICU read-data bus as a function of PLB-slave size, line-transfer size, and transfer order.
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R The ICU reads either the low 32 bits or the high 32 bits of the 64-bit interface, depending on the value of PLBC405ICURDWDADDR[1:3]. x When a 64-bit PLB slave responds, an aligned doubleword is sent from the slave to the ICU during each transfer cycle. Both words are read from the 64-bit interface by the ICU in this cycle. Table 2-10 shows the location of instructions on the ICU read-data bus as a function of PLBslave size, line-transfer size, and transfer order.
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R Chapter 2: Input/Output Interfaces transfer order is invalid if this signal asserted. The entries for a 32-bit PLB slave assume the connection to a 64-bit master shown in Figure 2-5, above.
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R Following reset, the processor block prevents the ICU from fetching instructions until the busy signal is deasserted for the first time. This is useful in situations where the processor block is reset by a core reset, but PLB devices are not reset. Waiting for the busy signal to be deasserted prevents fetch requests following reset from interfering with PLB activity that was initiated before reset.
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R Chapter 2: Input/Output Interfaces fastest rate at which a BIU can transfer instructions to the ICU (there is no limit to the number of cycles between two transfers). x All line transfers assume the target instruction (word) is returned first. Subsequent instructions in the line are returned sequentially by address, wrapping as necessary to the lower addresses in the same line.
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R Table 2-11: ISPLB Timing Diagram Abbreviations (Continued) Abbreviationa Description Where Used Subscripts Used to identify the instruction words returned by a transfer Read-data acknowledge ICU read-data bus ICU forward (bypass) (PLBC405ICURDDACK) (PLBC405ICURDDBUS[0:63]) # Used to identify the order doublewords are sent to the ICU Transfer order (PLBC405ICURDWDADDR[1:3]) a. The “#” symbol indicates a number.
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R Chapter 2: Input/Output Interfaces ISPLB Non-Pipelined Cacheable Sequential Fetch (Case 2) The timing diagram in Figure 2-7 shows two consecutive eight-word line fetches that are not address pipelined. The example assumes instructions are fetched sequentially from the end of the first line through the end of the second line. It provides an illustration of a transfer where the target instruction returned first by the BIU is not located at the start of the cache line.
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R The first line read (rl1) is requested by the ICU in cycle 3 in response to a cache miss (represented by the miss1 transaction in cycles 1 and 2). Instructions are sent from the BIU to the ICU fill buffer in cycles 4 through 7. Instructions in the fill buffer are bypassed to the instruction fetch unit to prevent a processor stall during sequential execution (represented by the byp1 transaction in cycles 5 through 8).
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R Chapter 2: Input/Output Interfaces After the first miss is detected, the ICU performs a prefetch in anticipation of requiring instructions from the next cache line (represented by the prefetch2 transaction in cycles 3 and 4). The second line read (rl2) is requested by the ICU in cycle 5 in response to the prefetch. After the first line is read from the BIU, instructions for the second line are sent from the BIU to the ICU fill buffer. This occurs in cycles 8 through 11.
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R in cycles 10 through 15). The line is not cacheable, so instructions are not transferred from the fill buffer to the instruction cache.
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R Chapter 2: Input/Output Interfaces Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLBCLK and CPMC405CLK ICU miss1 prefetch2 byp1 byp2 PPC405 Outputs: C405PLBICUREQUEST rl1 rl2 C405PLBICUABUS[0:29] adr1 adr2 PLB/BIU Outputs: PLBC405ICUADDRACK rl1 rl2 PLBC405ICURDDACK rl167 rl101 rl123 rl145 rl201 rl223 rl245 rl267 PLBC405ICURDDBUS[0:63] d167 d101 d123 d145 d201 d223 d245 d267 6 PLBC405ICURDWDADDR[1:3] 0 2 4 0 2 4 6 PLBC405ICUBUSY UG018_16_101701 Fi
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R ISPLB 3:1 Core-to-PLB Line Fetch The timing diagram in Figure 2-13 shows an eight-word line fetch in a system with a PLB clock that runs at one third the frequency of the PowerPC 405 clock. The line read (rl1) is requested by the ICU in PLB cycle 2, which corresponds to PowerPC 405 cycle 4. The BIU responds in the same cycle. Instructions are sent from the BIU to the ICU fill buffer in PLB cycles 3 through 6 (PowerPC 405 cycles 7 through 18).
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R Chapter 2: Input/Output Interfaces Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLBCLK and CPMC405CLK ICU miss1 miss2 PPC405 Outputs: C405PLBICUREQUEST rl1 rl2 C405PLBICUABUS[0:29] adr1 adr2 rl1 rl2 C405PLBICUABORT PLB/BIU Outputs: PLBC405ICUADDRACK PLBC405ICURDDACK rl201 rl223 rl245 rl267 PLBC405ICURDDBUS[0:63] d201 d223 d245 d267 0 PLBC405ICURDWDADDR[1:3] 2 4 6 PLBC405ICUBUSY UG018_17_101701 Figure 2-14: ISPLB Aborted Fetch Request Data-Side Proc
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R x The target address of the data to be accessed is specified by the address bus, C405PLBDCUABUS[0:31]. See “C405PLBDCUABUS[0:31] (Output)”. x The transfer size is specified as a single word or as eight words (cache line) using C405PLBDCUSIZE2. See “C405PLBDCUSIZE2 (Output)”. The remaining bits of the transfer size (0, 1, and 3) must be tied to zero at the PLB arbiter. x The byte enables for single-word accesses are specified using C405PLBDCUBE[0:7] (see “C405PLBDCUBE[0:7] (Output)”).
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R Chapter 2: Input/Output Interfaces i x An eight-word line transfer moves the eight-word cache line aligned on the address specified by C405PLBDCUABUS[0:26]. See “C405PLBDCUABUS[0:31] (Output)”. This cache line contains the target data accessed by the DCU. The cache line is transferred using four doubleword or eight word transfer operations, depending on the PLB slave bus width (64-bit or 32-bit, respectively).
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R An eight-word line-write transfer occurs when the fill buffer replaces an existing datacache line containing modified data. The existing cache line is written to memory before it is replaced with the fill-buffer contents. The write is performed using a separate PLB transaction than the previous transfer that caused the replacement. Execution of the dcbf and dcbst instructions also cause an eight-word line write. Address Pipelining The DCU can overlap a data-access request with a previous request.
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R Chapter 2: Input/Output Interfaces PPC405 PLBC405DCUADDRACK C405PLBDCUREQUEST PLBC405DCUSSIZE1 C405PLBDCURNW PLBC405DCURDDACK C405PLBDCUABUS[0:31] PLBC405DCURDDBUS[0:63] C405PLBDCUSIZE2 PLBC405DCURDWDADDR[1:3] C405PLBDCUCACHEABLE PLBC405DCUWRDACK C405PLBDCUWRITETHRU PLBC405DCUBUSY C405PLBDCUU0ATTR PLBC405DCUERR C405PLBDCUGUARDED C405PLBDCUBE[0:7] C405PLBDCUPRIORITY[0:1] C405PLBDCUABORT C405PLBDCUWRDBUS[0:63] UG018_05_102001 Figure 2-15: Data-Side PLB Interface Block Symbol Table 2-12: D
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R Table 2-12: Data-Side PLB Interface I/O Signal Summary (Continued) I/O Type If Unused Function PLBC405DCURDDACK I 0 Indicates the DCU read-data bus contains valid data for transfer to the DCU. PLBC405DCURDDBUS[0:63] I 0x0000_0000 _0000_0000 The DCU read-data bus used to transfer data from the PLB slave to the DCU. PLBC405DCURDWDADDR[1:3] I 0b000 PLBC405DCUWRDACK I 0 Indicates the data on the DCU write-data bus is being accepted by the PLB slave.
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R Chapter 2: Input/Output Interfaces If the transfer size is a single word, C405PLBDCUBE[0:7] is also valid when the request is asserted. These signals specify which bytes are transferred between the DCU and PLB slave. If the transfer size is an eight-word line, C405PLBDCUBE[0:7] is not used and must be ignored by the PLB slave. C405PLBDCUPRIORITY[0:1] is valid when the request is asserted. This signal indicates the priority of the data-access request.
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R An eight-word line transfer moves the cache line aligned on the address specified by C405PLBDCUABUS[0:26]. This cache line contains the target data accessed by the DCU. The cache line is transferred using four doubleword or eight word transfer operations, depending on the PLB slave bus width (64-bit or 32-bit, respectively). The words moved during an eight-word line transfer can be sent from the PLB slave to the DCU in any order (target-word-first, sequential, other).
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R Chapter 2: Input/Output Interfaces C405PLBDCUU0ATTR (Output) This signal reflects the value of the user-defined (U0) storage attribute for the target address. The accessed data is not in a memory location characterized by this attribute when the signal is deasserted (0). It is in a memory location characterized by this attribute when the signal is asserted (1). This signal is valid when the DCU is presenting a dataaccess request to the PLB slave.
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R 64-Bit PLB Master 32-Bit PLB Slave PLBC405DCURDDBUS[0:31] PLBC405DCURDDBUS[0:31] PLBC405DCURDDBUS[32:63] C405PLBDCUWRDBUS[0:31] C405PLBDCUWRDBUS[32:63] C405PLBDCUWRDBUS[0:31] Unconnected C405PLBDCUABUS[0:31] C405PLBDCUABUS[0:31] [29] C405PLBDCUBE[0:3] C405PLBDCUBE[0:3] C405PLBDCUBE[4:7] UG018_20_101501 Figure 2-16: Attachment of DSPLB Between 32-Bit Slave and 64-Bit Master Table 2-13 shows the possible values that can be presented by the byte enables and how they are interpreted by the PLB sl
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R Chapter 2: Input/Output Interfaces Table 2-13: Interpretation of DCU Byte Enables During Word Transfers (Continued) 32-Bit PLB Slave Data Bus 64-Bit PLB Slave Data Bus Byte Enables [0:7] Valid Bytes Bits Valid Bytes Bits 0000_0111 Bytes 1:3 8:31 Bytes 5:7 40:63 0000_0010 Byte 2 16:23 Byte 6 48:55 0000_0011 Bytes 2:3 (Halfword 1) 16:31 Bytes 6:7 (Halfword 3) 48:63 0000_0001 Byte 3 24:31 Byte 7 56:63 C405PLBDCUPRIORITY[0:1] (Output) These signals are used to specify the priority
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R an aborted data-write request. In this case, memory must not be updated by the PLB slave and no further write acknowledgements can be presented by the PLB slave for the aborted request. The DCU only aborts a data-access request when the processor is reset. Such an abort can occur during an address-pipelined data-access request while the PLB slave is responding to a previous data-access request.
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R Chapter 2: Input/Output Interfaces Table 2-15: Contents of DCU Write-Data Bus During Eight-Word Line Transfer PLB-Slave Size Transfer DCU Write-Data Bus [0:31] DCU Write-Data Bus [32:63] 32-Bit First Word 0 Not Applicable Second Word 1 Third Word 2 Fourth Word 3 Fifth Word 4 Sixth Word 5 Seventh Word 6 Eighth Word 7 First Word 0 Word 1 Second Word 2 Word 3 Third Word 4 Word 5 Fourth Word 6 Word 7 64-Bit PLBC405DCUADDRACK (Input) When asserted, this signal indicates t
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R must abort a DCU request (move no data) if the DCU asserts C405PLBDCUABORT in the same cycle the PLB slave acknowledges the request. The DCU supports up to three outstanding requests over the PLB (two read and one write). The DCU can make a subsequent request after the current request is acknowledged. The DCU deasserts C405PLBDCUREQUEST for at least one cycle after the current request is acknowledged and before the subsequent request is asserted.
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R Chapter 2: Input/Output Interfaces x During a single word write, the DCU replicates the data on the high and low words of the write data bus. The byte enables indicate which bytes on the high word or low word are valid and should be latched by the PLB slave. x During an eight-word line write, data is sent by the 64-bit master over the entire write-data bus. Table 2-15, page 80, shows the order data is transferred to a 64-bit PLB slave during an eight-word line write.
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R PLBC405DCURDWDADDR[1:3] (Input) These signals are used to specify the transfer order. They identify which word or doubleword of an eight-word line transfer is present on the DCU read-data bus when the PLB slave returns instructions to the DCU. The words returned during a line transfer can be sent from the PLB slave to the DCU in any order (target-word-first, sequential, other). The transfer-order signals are valid when the read-data acknowledgement signal (PLBC405DCURDDACK) is asserted.
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R Chapter 2: Input/Output Interfaces is transferred from the DCU to the PLB slave. If this signal is deasserted, valid data on the write data bus has not been latched by the PLB slave. Write-data acknowledgement is asserted for one cycle per transfer. There is no limit to the number of cycles between two transfers. The number of transfers (and the number of write-data acknowledgements) depends on the PLB slave size (specified by PLBC405DCUSSIZE1 and the line-transfer size (specified by C405PLBDCUSIZE2).
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R The PLB slave should latch error information in DCRs so that software diagnostic routines can attempt to report and recover from the error. A bus-error address register (BEAR) should be implemented for storing the address of the access that caused the error. A buserror syndrome register (BESR) should be implemented for storing information about cause of the error.
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R Chapter 2: Input/Output Interfaces x The DCU activity is shown only as an aide in describing the examples. The occurrence and duration of this activity is not observable on the DSPLB.
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R The second line read (rl2) is requested by the DCU in cycle 4. The BIU responds to this request after it has completed all transactions associated with the first request (rl1). Data is sent from the BIU to the DCU fill buffer in cycles 7 through 10. After all data associated with this line is read, it is transferred by the DCU from the fill buffer to the data cache. This is represented by the fill2 transaction in cycles 11 through 13.
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R Chapter 2: Input/Output Interfaces is sent from the BIU to the DCU fill buffer in cycle 7. The DCU uses the byte enables to select the appropriate bytes from the read-data bus. The data is not cacheable, so the fill buffer is not transferred to the data cache after this transaction is completed. The third line read (rl3) cannot be requested until the first request (rl1) is complete. The earliest this request can occur is in cycle 7.
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R The second word read (rw2) is requested by the DCU in cycle 7 and the BIU responds in the same cycle. A single word is sent from the BIU to the DCU in cycle 8. The DCU uses the byte enables to select the appropriate bytes from the read-data bus. The third word read (rw3) is requested by the DCU in cycle 12 and the BIU responds in the same cycle. A single word is sent from the BIU to the DCU in cycle 13. The DCU uses the byte enables to select the appropriate bytes from the read-data bus.
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R Chapter 2: Input/Output Interfaces The third line write (wl3) cannot be started until the second request (wl2) is complete. This request is made by the DCU in cycle 13 in response to the flush3 request. The BIU responds in the same cycle the request is made by the DCU. Data is sent from the DCU to the BIU in cycles 13 through 16.
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R Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLBCLK and CPMC405CLK DCU flush1 flush3 PPC405 Outputs: C405PLBDCUREQUEST wl1 ww2 wl3 C405PLBDCUABUS[0:31] adr1 adr2 adr3 C405PLBDCURNW C405PLBDCUSIZE2 C405PLBDCUBE[0:7] val C405PLBDCUWRDBUS[0:63] d101 d123 d145 d167 d2 d301 d323 d345 d367 PLB/BIU Outputs: PLBC405DCUADDRACK wl1 ww2 wl3 PLBC405DCURDDACK PLBC405DCURDDBUS[0:63] PLBC405DCURDWDADDR[1:3] PLBC405DCUWRDACK wl101 wl123 wl145 wl167 ww2 wl301 wl323
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R Chapter 2: Input/Output Interfaces Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLBCLK and CPMC405CLK DCU PPC405 Outputs: C405PLBDCUREQUEST ww1 ww2 ww3 C405PLBDCUABUS[0:31] adr1 adr2 adr3 C405PLBDCUBE[0:7] val val val C405PLBDCUWRDBUS[0:63] d1 d2 d3 ww1 ww2 ww3 ww1 ww2 ww3 C405PLBDCURNW C405PLBDCUSIZE2 PLB/BIU Outputs: PLBC405DCUADDRACK PLBC405DCURDDACK PLBC405DCURDDBUS[0:63] PLBC405DCURDWDADDR[1:3] PLBC405DCUWRDACK PLBC405DCUBUSY UG018_26_101701
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R Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLBCLK and CPMC405CLK DCU flush1 fill2 PPC405 Outputs: C405PLBDCUREQUEST wl1 rl2 ww3 C405PLBDCUABUS[0:31] adr1 adr2 adr3 C405PLBDCURNW C405PLBDCUSIZE2 C405PLBDCUBE[0:7] C405PLBDCUWRDBUS[0:63] val d3 d101 d123 d145 d167 PLB/BIU Outputs: PLBC405DCUADDRACK wl1 rl2 ww3 PLBC405DCURDDACK rl201 rl223 rl245 rl267 PLBC405DCURDDBUS[0:63] d201 d223 d245 d267 PLBC405DCURDWDADDR[1:3] PLBC405DCUWRDACK 0 wl101 wl123 wl1
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R Chapter 2: Input/Output Interfaces Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLBCLK and CPMC405CLK DCU fill4 PPC405 Outputs: C405PLBDCUREQUEST ww1 rw2 ww3 rl4 C405PLBDCUABUS[0:31] adr1 adr2 adr3 adr4 C405PLBDCUBE[0:7] val val val C405PLBDCUWRDBUS[0:63] d1 C405PLBDCURNW C405PLBDCUSIZE2 d3 PLB/BIU Outputs: PLBC405DCUADDRACK ww1 rw2 ww3 rl4 PLBC405DCURDDACK rw2 rl401 rl423 rl445 rl467 PLBC405DCURDDBUS[0:63] d2 d401 d423 d445 d467 PLBC405DCU
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R Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLBCLK and CPMC405CLK DCU flush3 fill2 PPC405 Outputs: C405PLBDCUREQUEST ww1 rl2 wl3 C405PLBDCUABUS[0:31] adr1 adr2 adr3 C405PLBDCURNW C405PLBDCUSIZE2 C405PLBDCUBE[0:7] val C405PLBDCUWRDBUS[0:63] d1 d301 d323 d345 d367 PLB/BIU Outputs: PLBC405DCUADDRACK ww1 rl2 wl3 PLBC405DCURDDACK rl201 rl223 rl245 rl267 PLBC405DCURDDBUS[0:63] d201 d223 d245 d267 PLBC405DCURDWDADDR[1:3] PLBC405DCUWRDACK 0 ww1 2 4 6
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R Chapter 2: Input/Output Interfaces Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CPMC405CLK PLBCLK DCU fill1 PPC405 Outputs: C405PLBDCUREQUEST rl1 C405PLBDCUABUS[0:31] adr1 C405PLBDCURNW C405PLBDCUSIZE2 C405PLBDCUBE[0:7] C405PLBDCUWRDBUS[0:63] PLB/BIU Outputs: PLBC405DCUADDRACK rl1 PLBC405DCURDDACK rl101 rl123 rl145 rl167 PLBC405DCURDDBUS[0:63] d101 d123 d145 d167 0 2 4 6 PLBC405DCURDWDADDR[1:3] PLBC405DCUWRDACK PLBC405DCUBUSY UG018_30_101701 Figu
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R Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CPMC405CLK PLBCLK DCU flush1 PPC405 Outputs: C405PLBDCUREQUEST wl1 C405PLBDCUABUS[0:31] adr1 C405PLBDCURNW C405PLBDCUSIZE2 C405PLBDCUBE[0:7] C405PLBDCUWRDBUS[0:63] d101 d123 d145 d167 wl123 wl145 wl167 PLB/BIU Outputs: PLBC405DCUADDRACK wl1 PLBC405DCURDDACK PLBC405DCURDDBUS[0:63] PLBC405DCURDWDADDR[1:3] PLBC405DCUWRDACK wl101 PLBC405DCUBUSY UG018_31_101701 Figure 2-27: DSPLB 3:1 Core-to-PLB Line Write DSPLB
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R Chapter 2: Input/Output Interfaces Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLBCLK and CPMC405CLK DCU flush1 PPC405 Outputs: C405PLBDCUREQUEST wl1 rl2 C405PLBDCUABUS[0:31] adr1 adr2 C405PLBDCURNW C405PLBDCUSIZE2 C405PLBDCUBE[0:7] C405PLBDCUWRDBUS[0:63] d101 d123 d145 d167 C405PLBDCUABORT PLB/BIU Outputs: PLBC405DCUADDRACK wl1 rl2 PLBC405DCURDDACK PLBC405DCURDDBUS[0:63] PLBC405DCURDWDADDR[1:3] PLBC405DCUWRDACK wl101 wl123 wl145 wl167 PLBC405DCUBUSY UG0
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R Internal Device Control Register (DCR) Interface The PowerPC 405 Processor block contains several internal device-control registers, which can be used to control, configure, and hold status for various functional units in the Processor block. These registers are accessed on internal DCR busses, which share their address range with the device-control registers accessed on the external DCR bus.
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R Chapter 2: Input/Output Interfaces In Virtex-II Pro/ProX, a DCR access addressing the internal DCR logic could be visible on the external DCR bus interface as an access. Virtex-4-FX In Virtex-4-FX processor blocks, there are four functional units that contain device-control registers: 1. The data-side OCM (DSOCM) controller, which contains the DSCNTL and DSARC registers. 2. The instruction-side OCM (ISOCM) controller, which contains the ISCNTL, ISARC, ISINIT, and ISFILL registers. 3.
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R blocks that are associated with each PowerPC. Thus, this interface is not available to the user for connection to the FPGA fabric. Figure 2-29 shows the block symbol for the dedicated EMAC DCR interface. EMACDCRACK PPC405 EMACDCRDATA DCREMACCLK DCREMACENABLER DCREMACREAD DCREMACWRITE DCREMACABUS DCREMACDBUS UG018_02_29_042304 Note: This block symbol is provided for completeness. Though not available to the user, the user will be able to see these signals when modeling the hardware.
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R Chapter 2: Input/Output Interfaces DCRABUS[0:9] DCR Slave 1 DCRDBUSOUT[0:31] DCRWRITE PowerPC 405 Block DCRREAD DCRs DCRACK OR CPMDCRCLK (for Virtex-4 only) DCR Slave 2 DCRs DCR Slave 3 DCRs DCRDBUSIN[0:31] UG018_52_042304 Note: Abbreviated signal names are used.
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R (CPMC405CLOCK), the access times out. No error is flagged on time-out. The processor just continues to execute the next instruction. Figure 2-31 illustrates a logical implementation of the DCR bus interface. This implementation enables a DCR slave to run at a different clock speed than the PowerPC 405. The acknowledge signal is latched and forwarded with the DCR bus. The bypass multiplexor minimizes data-bus path delays when the DCR is not selected.
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R Chapter 2: Input/Output Interfaces PPC405 DCRC405ACK C405DCRREAD DCRC405DBUSIN[0:31] C405DCRWRITE C405DCRABUS[0:9] C405DCRDBUSOUT[0:31] UG018_06_020702 Figure 2-32: Virtex-II Pro and Virtex-II ProX DCR Interface Block Symbol Table 2-21: Virtex-II Pro and Virtex-II ProX DCR Interface I/O Signals I/O Type If Unused C405DCRREAD O No Connect Indicates a DCR read request occurred. C405DCRWRITE O No Connect Indicates a DCR write request occurred.
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R Table 2-22: Virtex-4-FX DCR Interface Name Correlation with Virtex-II Pro/ProX (Continued) Virtex-4-FX Name Virtex-II Pro/ProX Name EXTDCRABUS[0:9] C405DCRABUS[0:9] EXTDCRDBUSOUT[0:31] C405DCRDBUSOUT[0:31] EXTDCRACK DCRC405ACK EXTDCRDBUSIN[0:31] DCRC405DBUSIN[0:31] External DCR Bus Interface I/O Signal Descriptions The following sections describe the operation of the DCR interface I/O signals. Signals are presented with both Virtex-II Pro and Virtex-4-FX names.
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R Chapter 2: Input/Output Interfaces The processor does not begin driving a new DCR address until the DCR acknowledge signal corresponding to the previous DCR access has been deasserted for at least one cycle. C405DCRDBUSOUT[0:31]/EXTDCRDBUSOUT[0:31] (Output) This write-data bus is driven by the processor block when a mtdcr or mfdcr instruction is executed. Its contents are valid only when a DCR write-request or DCR read-request is asserted.
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R DCR Interface 1:1 Clocking, Latched Acknowledge The example in Figure 2-33 assumes the following: x The PowerPC 405 and the peripheral containing the DCR are clocked at the same frequency. x The acknowledge signal is latched and forwarded with the DCR bus as shown in Figure 2-31, page 103. x After the acknowledge signal is asserted, it is not deasserted until the appropriate read-access or write-access request signal is deasserted.
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R Chapter 2: Input/Output Interfaces Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CPMC405CLOCK (Virtex-II Pro)/ CPMDCRCLK (Virtex-4 FX) DCR (FPGA) Clock PPC405 Outputs: DCRWRITE/DCRREAD DCRABUS[0:9] addr0 addr1 addr2 DCRDBUSOUT[0:31] data0 data1 data2 DCR Outputs: DCRACK data0 DCRDBUSIN[0:31] data1 data2 UG018_42_032504 Note: Abbreviated signal names are used.
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R DCR Interface 1:2 Clocking, Latched Acknowledge The example in Figure 2-36 assumes the following: x The PowerPC 405 DCR interface is clocked at half the frequency of the peripheral containing the addressed DCR. x The acknowledge signal is latched and forwarded with the DCR bus as shown in Figure 2-31, page 103. x After the acknowledge signal is asserted, it is not deasserted until the appropriate read-access or write-access request signal is deasserted.
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R Chapter 2: Input/Output Interfaces interrupts ahead of noncritical interrupts when they occur simultaneously (certain debug exceptions are handled at a lower priority). Critical interrupts use a different save/restore register pair (SRR2 and SRR3) than is used by noncritical interrupts (SRR0 and SRR1). This enables a critical interrupt to interrupt a noncritical-interrupt handler. The state saved by the noncritical interrupt is not overwritten by the critical interrupt.
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R EIC Interface I/O Signal Descriptions The following sections describe the operation of the EIC interface I/O signals. EICC405CRITINPUTIRQ (Input) When asserted, this signal indicates the EIC is requesting that the processor block respond to an external critical interrupt. When deasserted, no request exists. The EIC is responsible for collecting critical interrupt requests from other peripherals and presenting them as a single request to the processor block.
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R Chapter 2: Input/Output Interfaces JTAG Interface I/O Signal Descriptions The following sections describe the operation of the JTAG interface I/O signals. JTGC405TCK (Input) This input is the JTAG TCK (Test ClocK) signal. The TMS and TDI signals are latched on the rising edge of TCK, while TDO is valid on the falling edge of TCK. The maximum TCK frequency is one-half the CPMC405CLOCK frequency. JTGC405TMS (Input) This input is the JTAG TMS (Test Mode Select) signal.
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R C405JTGSHIFTDR (Output) This output is asserted (logic High) when the PPC405 TAP is in the Shift-DR state. Most designs do not require this signal and should leave it unconnected. C405JTGUPDATEDR (Output) This output is asserted (logic High) when the PPC405 TAP is in the Update-DR state. Most designs do not require this signal and should leave it unconnected.
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R Chapter 2: Input/Output Interfaces The six least significant bits of the parts Instruction Register always comprise the FPGA Instruction Register. The remaining bits are ignored unless the PPC405 cores are connected in series with the FPGA JTAG logic, as described in the “Connecting PPC405 JTAG Logic in Series with the Dedicated Device JTAG Logic” section below.
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R The PPC405 cores do not have their own BSDL files; instead, the necessary INSTRUCTION_OPCODES and other information are incorporated in the device BSDL file. The PPC405 cores are not available for interconnect tests (i.e., EXTEST, SAMPLE/PRELOAD), as they do not have a boundary scan register. All device boundary scan tests are performed through the FPGA boundary scan register.
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R Chapter 2: Input/Output Interfaces PPC405 Core TDI JTGC405TDI TMS TDO C405JTGTDO JTGC405TMS TCK JTGC405TCK C405JTGTDOEN JTGC405TRSTNEG TRST PPC405 Core TDI JTGC405TDI TMS JTGC405TMS TCK JTGC405TCK TDO C405JTGTDO C405JTGTDOEN JTGC405TRSTNEG TRST TDI TMS TCK TDI TMS TDO TDO TCK UG018_75_032504 Figure 2-42: 116 Correct Wiring of JTAG Chains with Individual PPC405 Connections (Separate JTAG Chains) www.xilinx.
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R PPC405 Core TDI JTGC405TDI TMS C405JTGTDO JTGC405TMS TCK JTGC405TCK C405JTGTDOEN JTGC405TRSTNEG TRST PPC405 Core JTGC405TDI TDO C405JTGTDO JTGC405TMS JTGC405TCK C405JTGTDOEN JTGC405TRSTNEG TDI TMS TCK TDI TMS TDO TDO TCK UG018_72_032504 Figure 2-43: Correct Wiring of JTAG Chains with Individual PPC405 JTAG Connections (Internally Chained PPC405 Cores) PowerPC™ 405 Processor Block Reference Guide UG018 (v2.0) August 20, 2004 www.xilinx.
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R Chapter 2: Input/Output Interfaces 1 TDI 0 1 PPC405 Core 1 TMS 0 1 JTGC405TDI C405JTGTDO JTGC405TMS 1 TCK 1 TRST C405JTGTDOEN JTGC405TCK 0 1 JTGC405TRSTNEG 0 1 SEL SEL 1 0 1 1 0 TDO PPC405 Core 1 0 1 JTGC405TDI C405JTGTDO JTGC405TMS TDI TMS TCK 1 0 1 1 0 1 C405JTGTDOEN JTGC405TCK JTGC405TRSTNEG TDI TDO TDO TMS TCK UG018_73_032504 Figure 2-44: 118 Correct Wiring of JTAG Chain with Multiplexed PPC405 Connection www.xilinx.
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R Connecting PPC405 JTAG Logic in Series with the Dedicated Device JTAG Logic An alternative to connecting the PPC405 JTAG logic directly to programmable I/O is to wire it in series with the dedicated device JTAG logic. This is done by wiring the JTAG signals on the PPC405 core to a special design element called the JTAGPPC primitive in the user design.
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R Chapter 2: Input/Output Interfaces FPGA PPC405 Core JTGC405TDI C405JTGTDO JTGC405TMS JTGC405TCK C405JTGTDOEN JTGC405TRSTNEG PPC405 Core JTGC405TDI C405JTGTDO JTGC405TMS JTGC405TCK C405JTGTDOEN TCK TMS JTGC405TRSTNEG JTAGPPC Primitive TDIPPC TDOPPC TMS TDOTSPPC TCK vcco TDI TMS TCK TDO TDI 200Ω TDO TMS TCK UG018_74_040604 Figure 2-45: PPC405 Core JTAG Logic Connected in Series with FPGA JTAG Logic Using the JTAGPPC Primitive When the PPC405 JTAG logic is connected in series with t
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R For devices with more than one PPC405 core, users must connect the JTAG logic for ALL of the PPC405 cores on the device when using this connection style, even if some are not otherwise used. The JTAG signals are the only signals on unused PPC405 cores need to be connected. The PPC405 core that first sees TDI from the JTAGPPC primitive recognizes the first four most significant bits in the Instruction Register; the next PPC405 core sees the next four most significant bits, and so on.
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R Chapter 2: Input/Output Interfaces ); end component begin -- Component Instantiation U_PPC1 : PPC405 port map ( ... JTGC405TCK => TCK_IN, JTGC405TDI => TDI_IN, JTGC405TMS => TMS_IN, JTGC405TRSTNEG => TRSTNEG_IN, C405JTGTDO => TDO_OUT, JTGC405BNDSCANTDO => open, C405JTGTDOEN => open, C405JTGEXTEST => open, C405JTGCAPTUREDR => open, C405JTGSHIFTDR => open, C405JTGUPDATEDR=> open, C405JTGPGMOUT=> open, ...
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R .C405JTGSHIFTDR (), .C405JTGUPDATEDR (), .C405JTGPGMOUT (), ... ); endmodule; -- Module: SINGLE_PPC_JTAG_SERIAL -- Description: VHDL instantiation template for serial connection of a -- single PPC405 core to dedicated JTAG logic library IEEE; use IEEE.std_logic_1164.all; entity SINGLE_PPC_JTAG_SERIAL is port ( ); end SINGLE_PPC_JTAG_SERIAL; architecture SINGLE_PPC_JTAG_SERIAL_arch of SINGLE_PPC_JTAG_SERIAL is -- Component Declaration component PPC405 port( ...
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R Chapter 2: Input/Output Interfaces signal signal signal signal TDO_PPC TMS_PPC TDI_PPC TCK_PPC : : : : std_logic; std_logic; std_logic; std_logic; begin -- Component Instantiation U_PPC1 : PPC405 port map ( ... JTGC405TCK => TCK_PPC, JTGC405TDI => TDI_PPC, JTGC405TMS => TMS_PPC, JTGC405TRSTNEG => 1, C405JTGTDO => TDO_PPC, JTGC405BNDSCANTDO => open, C405JTGTDOEN => TDO_TS_PPC, C405JTGEXTEST => open, C405JTGCAPTUREDR => open, C405JTGSHIFTDR => open, C405JTGUPDATEDR=> open, 05JTGPGMOUT=> open, ...
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R .C405JTGTDO (TDO_PPC), .JTGC405BNDSCANTDO (), .C405JTGTDOEN (TDO_TS_PPC), .C405JTGEXTEST (), .C405JTGCAPTUREDR (), .C405JTGSHIFTDR (), .C405JTGUPDATEDR (), .C405JTGPGMOUT (), ... ); JTAGPPC U_JTAG( TDOTSPPC (TDO_TS_PPC), TDOPPC (TDO_PPC), TMS (TMS_PPC), TDIPPC (TDI_PPC), TCK (TCK_PPC) ); endmodule; -- Module: TWO_PPC_JTAG_SERIAL -- Description: VHDL instantiation template for serial connection of -- two PPC405 cores to dedicated JTAG logic library IEEE; use IEEE.std_logic_1164.
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R Chapter 2: Input/Output Interfaces component JTAGPPC port( TDOTSPPC : in std_logic; TDOPPC : in std_logic; TMS : out std_logic; TDIPPC : out std_logic; TCK : out std_logic; ); end component; signal signal signal signal signal signal signal signal TDO_TS_PPC : std_logic; TMS_PPC : std_logic; TDI_PPC : std_logic; TCK_PPC : std_logic; TDO_OUT1 : std_logic; TDO_OUT2 : std_logic; TDO_TS_OUT1 : std_logic; TDO_TS_OUT2 : std_logic; begin TDO_TS_PPC <= TDO_TS_OUT1 OR TDO_TS_OUT2; -- Component Instantiation U_P
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R U_JTAG : JTAGPPC port map ( TDOTSPPC => TDO_TS_PPC, TDOPPC => TDO_OUT2, TMS => TMS_PPC, TDIPPC => TDI_PPC, TCK => TCK_PPC ); end TWO_PPC_JTAG_SERIAL_arch; // Module: TWO_PPC_JTAG_SERIAL // Description: Verilog instantiation template for serial connection of // two PPC405 cores to dedicated JTAG logic module TWO_PPC_JTAG_SERIAL (); wire wire wire wire wire wire wire wire TDO_TS_PPC; TMS_PPC; TDI_PPC; TCK_PPC; TDO_OUT1; TDO_OUT2; TDO_TS_OUT1; TDO_TS_OUT2; or o1(TDO_TS_PPC, TDO_TS_OUT1, TDO_TS_OUT2); //
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R Chapter 2: Input/Output Interfaces .JTGC405BNDSCANTDO (), .C405JTGTDOEN (TDO_TS_OUT2), .C405JTGEXTEST (), .C405JTGCAPTUREDR (), .C405JTGSHIFTDR (), .C405JTGUPDATEDR (), .C405JTGPGMOUT (), ... ); JTAGPPC U_JTAG( TDOTSPPC (TDO_TS_PPC), TDOPPC (TDO_OUT2), TMS (TMS_PPC), TDIPPC (TDI_PPC), TCK (TCK_PPC) ); endmodule; Debug Interface The debug interface enables an external debugging tool (such as RISCWatch) to operate the PowerPC 405 debug resources in external-debug mode.
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R Table 2-26: Debug Interface I/O Signals I/O Type If Unused DBGC405EXTBUSHOLDACK I 0 Indicates the bus controller has given control of the bus to an external master. DBGC405DEBUGHALT I 0 Indicates the external debug logic is placing the processor in debug halt mode. DBGC405UNCONDDEBUGEVENT I 0 Indicates the external debug logic is causing an unconditional debug event. C405DBGWBFULL O No Connect Indicates the PowerPC 405 writeback pipeline stage is full.
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R Chapter 2: Input/Output Interfaces In systems that deactivate the clocks to manage power, the debug halt signal should be used to restart the clocks (if stopped) to enable an external debugger to operate the processor. After the debugger finishes its operation and deasserts the debug halt signal, the clocks can be stopped to return the processor to sleep mode. This is a positive active signal. However, the debug halt signal produced by the RISCWatch debugger is negative active.
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R C405DBGSTOPACK (Output) When asserted, this signal indicates that the PowerPC 405 is in debug halt mode. When deasserted, the processor is not in debug halt mode. C405DBGLOADDATAONAPUDBUS (Output, Virtex-4-FX only) This signal is asserted when there is a valid load data being transferred between the APU controller logic and the PowerPC 405 core. Trace Interface The processor uses the trace interface when operating in real-time trace-debug mode.
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R Table 2-27: Chapter 2: Input/Output Interfaces Trace Interface Signals Signal I/O Type If Unused Function C405TRCTRIGGEREVENTOUT O Wrap to Trigger Event In Indicates a trigger event occurred. C405TRCTRIGGEREVENTTYPE[0:10] O No Connect Specifies which debug event caused the trigger event. C405TRCCYCLE O No Connect Specifies the trace cycle. C405TRCEVENEXECUTIONSTATUS[0:1] O No Connect Specifies the execution status collected during the first of two processor cycles.
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R Table 2-28: Purpose of C405TRCTRIGGEREVENTTYPE[0:10] Signals Bit Debug Event 0 Instruction Address Compare 1 (IAC1) 1 Instruction Address Compare 2 (IAC2) 2 Instruction Address Compare 3 (IAC3) 3 Instruction Address Compare 4 (IAC4) 4 Data Address Compare 1 (DAC1)—Read 5 Data Address Compare 1 (DAC1)—Write 6 Data Address Compare 2 (DAC2)—Read 7 Data Address Compare 2 (DAC2)—Write 8 Trap Instruction (TDE) 9 Exception Taken (EDE) 10 Unconditional (UDE) FPGA logic can combine these
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R Chapter 2: Input/Output Interfaces C405TRCTRACESTATUS[0:3] (Output) These signals provide additional information required by a trace tool when reconstructing an instruction execution sequence. This information is collected every processor cycle, but it is made available to the trace interface once every two cycles. The information collected during those two cycles is broadcast over the trace interface in a single trace cycle.
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R Table 2-29: PVR Interface I/O Signals I/O Type If Unused TIEPVRBIT8 I No Connect Set bit 8 in Processor Version Register (OWN field) TIEPVRBIT9 I No Connect Set bit 9 in Processor Version Register (OWN field) TIEPVRBIT10 I No Connect Set bit 10 in Processor Version Register (OWN field) TIEPVRBIT11 I No Connect Set bit 11 in Processor Version Register (OWN field) TIEPVRBIT28 I No Connect Set bit 28 in Processor Version Register (AID field) TIEPVRBIT29 I No Connect Set bit 29 in P
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R Chapter 2: Input/Output Interfaces Additional FPGA Specific Signals Figure shows the block symbol for the additional FPGA signals used by the processor block. The signals are summarized in Table 2-30. MCBCPUCLKEN PPC405 MCBJTAGENT MCBTIMEREN MCPPCRST UG018_02_49_032504 Figure 2-49: Table 2-30: FPGA Specific Interface Block Symbol Additional FPGA I/O Signals I/O Type If Unused Function MCBCPUCLKEN I 1 Indicates the PowerPC 405 clock enable should follow GWE during a partial reconfiguration.
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R MCBTIMEREN (Input) When asserted, this signal indicates that the enable for the timer clock zone (CPMC405TIMERCLKEN) should follow (match the value of) the global write enable (GWE) during the FPGA startup sequence. When deasserted, the enable for the timer clock zone ignores (is independent of) the value of GWE.
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R 138 Chapter 2: Input/Output Interfaces www.xilinx.com 1-800-255-7778 PowerPC™ 405 Processor Block Reference Guide UG018 (v2.
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R Chapter 3 PowerPC 405 OCM Controller Introduction The On-Chip Memory (OCM) controller serves as a dedicated interface between the FPGA BRAMs and the OCM signals contained within the embedded PPC405 core. The OCM controller provides non-cacheable access to instruction-side and data-side memory spaces. The data-side interface supports a 32-bit, bi-directional memory interface, and the instruction-side interface supports a 64-bit unidirectional memory interface.
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R Chapter 3: PowerPC 405 OCM Controller Comparison of Virtex-II Pro and Virtex-4 OCM Controllers The Virtex-4 OCM controller is completely backward compatible with the Virtex-II Pro OCM controller. Table 3-1 highlights the new features available only on the Virtex-4 OCM controller. Detailed discussion of these features will be provided later in this chapter.
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R Features for Instruction-Side OCM (ISOCM) The ISOCM interface contains a 64-bit read only port for instruction fetches and a 32-bit read and write port to initialize or test the ISBRAM. x 64-bit Data Read Only bus (two BRAM clock cycles) x For Virtex-II Pro, 32-bit Data Write Only bus through DCR instruction. For Virtex-4, 32-bit Data Read and Write bus through DCR instruction. x Separate 21-bit read only and write only addresses to ISBRAM. x DCR registers: ISCNTL, ISARC, ISINIT, ISFILL.
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R Chapter 3: PowerPC 405 OCM Controller Table 3-2: DSOCM and ISOCM Features (Continued) Data-Side OCM Interface Feature Instruction-Side OCM Interface Clock Ratio (PPC405:OCM) Virtex-II Pro Integer: 1:1 through 4:1 Integer: 1:1 through 4:1 Virtex-4 1:1 through 8:1 1:1 through 8:1 Clock ratio automatic detection. Virtex-4 only Virtex-4 only Variable Latency Read/Write Virtex-4 only Not applicable Initialize block BRAM during FPGA device configuration.
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R up with the value on the input ports: DSARCVALUE[0:7] and ISARCVALUE[0:7] respectively. The two registers can also be loaded using DCR write assembly instructions (mtdcr). The value of DSARC and ISARC defines the most significant eight address bits for the two 16 MB memory spaces (instruction and data) available on the OCM, assuming OCM address decoding is enabled in bit 0 of the ISCNTL/DSCNTL registers.
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R Chapter 3: PowerPC 405 OCM Controller register defines the 16 MB memory region that is valid for the DSOCM. Load instructions have a priority over store instructions at the DSOCM interface Non-Memory Peripherals for DSOCM The OCM interface is designed to connect to memory. To correctly implement nonmemory peripherals that attach to DSOCM, designers must be aware of two OCM specific behaviors: execution re-ordering and store-data bypass.
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R DSOCM Ports Figure 3-2 and Figure 3-3 are the block diagrams of the DSOCM in Virtex-4 and Virtex-II Pro. All signals are in big endian format. DSOCMBRAMABUS[8:29] BRAMDSOCMRDDBUS[0:31] BRAMDSOCMCLK DSOCMBRAMWRDBUS[0:31] DSOCMRDWRCOMPLETE DSOCMBRAMBYTEWRITE[0:3] (Virtex-4 Only) Clock & Reset are same signals that go into CPU; therefore, no separate Clock & Reset are required.
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R Chapter 3: PowerPC 405 OCM Controller DSOCM Input Ports Table 3-3 describes the Data Side OCM (DSOCM) input ports. Table 3-3: DSOCM Input Ports Port BRAMDSOCMCLK Direction Input Description This signal clocks the DSOCM controller and the data side interface logic (Virtex-4 only) or memory located in the FPGA fabric. When in multi-cycle mode, the processor clock is in an N:1 ratio with BRAMDSOCMCLK.
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R DSOCM Input Ports: Attributes Attributes are inputs to the OCM controller from the FPGA fabric that must be connected to initialize registers at FPGA power up, or following a processor reset. These inputs are used to: x Define the DSOCM control register DCR addresses in the DCR memory space. x Define the 16MB memory locations for the DSOCM controller. x Enable the DSOCM address decoder. x Define the operating characteristics for the bus interface circuitry.
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R Chapter 3: PowerPC 405 OCM Controller DSOCM Output Ports Table 3-5 describes the data-side OCM (DSOCM) output ports. Table 3-5: DSOCM Output Ports Port Direction Description DSOCMBRAMEN Output This is the BRAM enable signal that is asserted for both reads and writes to the data-side memory interface. This signal is asserted for one and only one BRAMDSOCMCLK cycle. DSOCMBRAMABUS[8:29] contains the address and DSOCMBRAMWRDBUS[0:31] contains the data (for write).
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R Table 3-5: DSOCM Output Ports (Continued) Port DSOCMRDADDRVALID Direction Description Output This signal is used when the DSOCM controller is connected to the logic in the FPGA fabric (e.g. memory-mapped peripheral) with a variable latency. The signal indicates a read access and indicates the read address is valid on the DSOCMBRAMABUS[8:29]. This signal will be asserted for one BRAMDSOCMCLK cycle only.
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R Chapter 3: PowerPC 405 OCM Controller (RAMB16S9S9) X 4 DSOCMBRAMABUS[19:29] ADDRA[10:0] DIA[7:0] DSOCMBRAMWRDBUS[0:31] DSOCMBRAMBYTEWRITE[0:3] DOA[7:0] WEA CLKA BRAMDSOCMCLK Global signals from FPGA system interface SSRA DSOCMBRAMEN BRAMDSOCMRDDBUS[0:31] *ENA can be tied off permanently for higher performance.
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R (RAMB16S9S9) X 4 DSOCMBRAMABUS[19:29] ADDRA[10:0] DSOCMBRAMWRDBUS[0:31] DIA[7:0] DOA[7:0] DSOCMBRAMBYTEWRITE[0:3] WEA CLKA BRAMDSOCMCLK Global signals from FPGA system interface SSRA DSOCMBRAMEN *ENA can be tied off permanently for higher performance.
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R Chapter 3: PowerPC 405 OCM Controller Figure 3-6 shows the extended feature in Virtex-4 for DSOCM-to-Memory-Mapped-SlavePeripheral interface.
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R BRAMISOCMRDDBUS[0:63] ISOCMBRAMRDABUS[8:28] BRAMISOCMCLK ISOCMBRAMWRABUS[8:28] BRAMISOCMDCRRDBUS[0:31] (Virtex-4 Only) ISOCMBRAMWRDBUS[0:31] Clock & Reset are same signals that go into CPU; therefore, no separate Clock & Reset are required.
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R Chapter 3: PowerPC 405 OCM Controller ISOCM Input Ports, Attributes Attributes are inputs to the OCM controller, from the FPGA fabric, that must be connected to initialize control registers at FPGA power-up, or following a PPC405 reset. The ISINIT and ISFILL registers cannot be initialized in this manner. These registers are initialized only through “move to DCR” (mtdcr) instructions. Application software can also modify the contents of the ISARC and ISCNTL registers using mtdcr and mfdcr instructions.
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R ISOCM Output Ports Table 3-8 describes the instruction-side OCM (ISOCM) output ports. Table 3-8: ISOCM Output Ports Port Direction Description ISOCMBRAMEN Output This is a BRAM read enable from the ISOCM controller. This signal is asserted only for valid ISOCM instruction fetch cycles. For the fastest memory access applications, the BRAM enable input (EN) can be locally tied to a logic 1 level.
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R Table 3-8: Chapter 3: PowerPC 405 OCM Controller ISOCM Output Ports (Continued) Port ISOCMBRAMEVENWRITEEN Direction Output Description Note: Optional. Used in dual-port BRAM interface designs only. Write enable to qualify a valid write into a block RAM via a DCRbased access. This signal enables a write into the 32-bit memory that contains even instruction words BRAMISOCMRDDBUS[0:31].
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R Figure 3-9 shows an example of an ISOCM-to-BRAM interface in Virtex-II Pro. Figure 3-10 shows an example of an ISOCM-to-BRAM interface in Virtex-4.
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R Chapter 3: PowerPC 405 OCM Controller (RAMB16S18S18) X 4 (2 for Odd words, 2 for Even) ISOCMBRAMRDABUS[19:28] ADDRB[9:0] DOB[15:0] BRAMISOCMRDDBUS[0:63] WEB BRAMISOCMCLK CLKB ISOCMBRAMEN ENB* Global signals from FPGA system interface SSRB PORT B ISOCMDCRBRAMRDSELECT ADDRA[13:4] ISOCMBRAMWRABUS[19:28] DIA[15:0] ISOCMBRAMWRDBUS[0:31] ISOCMBRAMODDWRITEEN ISOCMBRAMEVENWRITEEN WEA ISCNTLVALUE[0:7] CLKA ISARCVALUE[0:7] ENA* ISOCMDCRBRAMEVENEN ISOCMDCRBRAMODDEN SSRA *ENA can be tied off p
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R locations. These bits are decoded against PPC405 address bits 0:7. These eight most significant address bits permit the OCM controllers to reside independently in any 16 MB, non-cacheable, memory range within the PPC405 32bit address (4 GB) memory space The ISOCM and DSOCM hardware outputs a maximum of 22 address bits (data-side address bits [8:29] and instruction-side address bits [8:28]) to address memory contained in the FPGA fabric.
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R Table 3-10: Chapter 3: PowerPC 405 OCM Controller DSCNTL Register for Virtex-4 Bit 0 DSOCM Enable If set to 1, address decoding based on the value of DSARC will be enabled. If set to 0, the content in DSARC will be ignored. Bit 1 DISABLEOPERANDFWD If set to 1, load data from the DSOCM goes directly into a latch in the processor block.
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R Table 3-12: ISCNTL Register for Virtex-4 Bit 0 ISOCM Enable If set to 1, address decoding based on the value of ISARC will be enabled. If set to 0, the content in ISARC will be ignored. Bit 1 Reserved. This bit must be configured to 0. Bit 2 Enable DCR Based Read Back If this bit is set to 1, reading from ISFILL register using an mfdcr instruction will return the memory content addressed by ISINIT register.
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R Chapter 3: PowerPC 405 OCM Controller User Programmable Registers Allocated within DCR address space (Programmer's Model) DSARC (DSOCM Address Range Compare Register) 0 1 2 3 4 5 6 7 A0/P A1/P A2/P A3/P A4/P A5/P A6/P A7/P 1 2 3 4 5 D0/P D1/P D2/P D3/P D4/P D5/P... Note: The top 8 bits of the CPU address are compared with DSARC to provide a 16 MB logical address space for DSOCM block. OCM must be placed in a non-cacheable memory region. 8 bits: Control Register for DSOCM.
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R User Programmable Registers Allocated within DCR address space (Programmer's Model) DSARC (DSOCM Address Range Compare Register) 0 1 2 3 4 5 6 7 A0/P A1/P A2/P A3/P A4/P A5/P A6/P A7/P 1 2 3 4 5 D0/P D1/P D2/P D3/P D4/P ... Note: The top 8 bits of the CPU address are compared with DSARC to provide a 16 MB logical address space for DSOCM block. OCM must be placed in a non-cacheable memory region. 8 bits: Control Register for DSOCM.
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R Chapter 3: PowerPC 405 OCM Controller User Programmable Registers Allocated within DCR address space (Programmer's Model) ISARC (ISOCM Address Range Compare Register) 0 1 2 3 4 5 6 7 A0/P A1/P A2/P A3/P A4/P A5/P A6/P A7/P 1 D0/P D1/P... 2 3 4 5 D4/P D5/P... Note: The top 8 bits of the CPU address are compared with ISARC to provide a 16 MB logical address space for ISOCM block. OCM must be placed in a non-cacheable memory region. 8 bits: Control Register for ISOCM.
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R User Programmable Registers Allocated within DCR address space (Programmer's Model) ISARC (ISOCM Address Range Compare Register) 0 1 2 3 4 5 6 7 A0/P A1/P A2/P A3/P A4/P A5/P A6/P A7/P 1 2 3 D0/P D1/P... D2/P D3/P 4 5 D4/P ... Note: The top 8 bits of the CPU address are compared with ISARC to provide a 16 MB logical address space for ISOCM block. OCM must be placed in a non-cacheable memory region. 8 bits: Control Register for ISOCM.
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R Chapter 3: PowerPC 405 OCM Controller DCR Write Access As shown in Figure 3-15, ISINIT is a 22-bit register (A8-A29) that is mapped to DCR write data bus bits D8-D29. The write address on the memory interface is A8-A28, and address bit A29 is used to control the ISOCMBRAMODDWRITEEN and ISOCMBRAMEVENWRITEEN signals. Additionally, in Virtex-4, the ISOCMDCRBRAMEVENEN and ISOCMDCRBRAMODDEN signals can be used to select the corresponding BRAMs in which to write.
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R DCR Read Access If the ISINIT register is read back on the DCR: x For Virtex-II Pro, bits A8-A29 are mapped onto DCR read data bus bits D0-D21 as shown in Figure 3-16, please note that the mapping for read access is different from write. x For Virtex-4, if bit 2 of ISENTL is set to 1, bits A8-A29 are mapped onto DCR read bus bits D8-D29, as shown in Figure 3-17. This helps to eliminate bit shifting in software for further operation on the DCR read value of the ISINIT register.
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R Chapter 3: PowerPC 405 OCM Controller ISINIT (ISOCM Initialization Address) Read Data on DCRDBUS D0 D1 .... D 19 D 20 D 21 Content in ISINIT Register Bit 8 Bit 9 .... Bit 27 Bit 28 Bit 29 .... A 27 A 28 A 29 Map to physical address bus to ISBRAM ISOCMBRAMWRABUS[ 8:28 ] A8 A9 Bit 0 to Bit 21 ISINIT register value maps to 21 bit initialization address for ISOCMBRAMWRABUS [ 8:28 ]. This address is incremented by 1 for every write into ISFILL register.
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R ISINIT (ISOCM Initialization Address) Read Data on DCRDBUS D8 D9 .... D 27 D 28 D 29 Content in ISINIT Register Bit 8 Bit 9 .... Bit 27 Bit 28 Bit 29 .... A 27 A 28 A 29 Map to physical address bus to ISBRAM ISOCMBRAMWRABUS[ 8:28 ] A8 A9 Bit 8 to Bit 28 of ISINIT register value maps to 21 bit initialization address for ISOCMBRAMWRABUS [ 8:28 ]. The address represented by A8 to A29 is increased by 1 for every write into the ISFILL register.
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R Chapter 3: PowerPC 405 OCM Controller routing delays, signal loading, BRAM memory access time, clock to output times, and setup and hold times of the BRAM and processor blocks. Users may need to go through multiple iterations of evaluating OCM BRAM size versus OCM clock frequency in order to achieve the optimum performance. The clock ratio between the BRAM clock and the PPC405 is auto-detected in Virtex-4 when control register bit 3 is set to 1 (DSCNTL and ISCNTL).
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R ISOCM 1:1 Instruction Fetch Timing CPMC405Clock BRAMISOCMCLK Load Address (To BRAM) Read Data (From BRAM) L_addr_1 L_addr_2 Rd_data_1 L_addr_3 Rd_data_2 L_addr_4 Rd_data_3 Rd_data_4 UG018_60_030603 Figure 3-18: Instruction Fetch Timing In multi-cycle mode, initial wait cycles are inserted until the CPMC405CLOCK and BRAMISOCMCLK rising edges are aligned. After the initial startup latency, two instructions (64 bits) can be fetched every two BRAM clock cycles.
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R Chapter 3: PowerPC 405 OCM Controller In order to estimate the theoretical maximum number of instruction fetches per second on the OCM interface, measure the period of the BRAM clock cycle to determine the maximum throughput.
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R mode and multi-cycle Mode. The timing interface between the OCM controller and the memory is always with respect to the BRAMISOCMCLK.
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R Chapter 3: PowerPC 405 OCM Controller ISOCM 2:1 Write Timing CPMC405Clock BRAMISOCMCLK Clock to Valid Addr Out BRAM latches in data Write Address (To BRAM) W_addr Clock to Valid Data Out Write Data (To BRAM) W_data Clock to Valid Write Enable (To BRAM) OddWriteEn or EvenWriteEn UG018_67_030603 Figure 3-21: Multi Cycle Mode (2:1) ISOCM Write Timing DSOCM Data Load, Fixed Latency Figure 3-22 and Figure 3-23 show two back-to-back loads for single-cycle mode and multicycle mode with a CPMC405C
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R DSOCM 1:1 Data Load Timing CPMC405Clock BRAMDSOCMCLK Load Address (To BRAM) L_addr_1 Read Data (From BRAM) L_addr_2 Rd_data_1 L_addr_3 Rd_data_2 L_addr_4 Rd_data_3 Rd_data_4 UG018_62_030603 Figure 3-22: Single Cycle Mode (1:1) Data Load Timing In multi-cycle mode, initial wait cycles are inserted until the CPMC405CLOCK and BRAMDSOCMCLK rising edges are aligned. After the initial startup latency, one load (32 bits) can be completed every two BRAMDSOCMCLK clock cycles.
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R Chapter 3: PowerPC 405 OCM Controller In the figures above, L_addr_n refers to the OCM controller address outputs DSOCMBRAMRDADDR and Rd_data_n refers to the OCM controller data bus inputs BRAMDSOCMRDDBUS from the DSBRAMs DSOCM Store, Fixed Latency Figure 3-24 and Figure 3-25 below show two back-to-back stores for single-cycle mode and multi-cycle mode with a CPMC405CLOCK:BRAMDSOCMCLK ratio of 2:1.
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R period should be used. Note that this is only an estimate of store performance on the interface. DSOCM 2:1 Data Store Timing CPMC405Clock BRAMDSOCMCLK Store Address (To BRAM) S_addr_1 S_addr_2 Write Data (To BRAM) St_data_1 St_data_2 UG018_65_040403 Figure 3-25: Multi Cycle Mode (2:1) Data Store Timing In the figures above, S_addr_n refers to the OCM controller address outputs DSOCMBRAMWRADDR and St_data_n refers to the OCM controller data bus outputs BRAMDSOCMWRDBUS to the DSBRAMs.
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R Chapter 3: PowerPC 405 OCM Controller DSOCM Data Load, Variable Latency Figure 3-26 and Figure 3-27 show two load operations with variable latency for single cycle mode and multi-cycle mode with a CPMC405CLOCK:BRAMDSOCMCLK ratio of 2:1. In both single-cycle mode and multi-cycle mode, the data load operation consists of the following sequence: 1. The CPU launches the load request to the OCM controller. 2.
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R DSOCM 2:1 Data Store Timing (Variable latency, DSOCMRDWRCOMPLETE driven by OCM slaves) CPMC405Clock BRAMDSOCMCLK Load Address (To BRAM or Slave) L_addr_1 Both DSOCMBRAMEN and DSOCMRDADDRVALID as rd addr valid (To BRAM or Slave) Read addr valid L_addr_2 rd addr Read Data (To BRAM or Slave) Read Complete (From BRAM or Slave) next valid Rd_data_1 Rd_data_2 complete complete UG018_63c_112103 Figure 3-27: Multi Cycle Mode (2:1) DSOCM Read Variable Latency Virtex-4 DSOCM Data Store, Variable La
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R Chapter 3: PowerPC 405 OCM Controller DSOCM 1:1 Data Store Timing (Variable latency, DSOCMRDWRCOMPLETE driven by OCM slaves) CPMC405Clock BRAMDSOCMCLK DSOCMBRAMBYTEWRITE[0:3] (To BRAM or Slave) Byte_wr_1 Byte_wr_2 Store Address (To BRAM or Slave) S_addr_1 S_addr_2 Write Data (To BRAM or Slave) St_data_1 St_data_2 valid next valid DSOCMWRADDRVALID (To BRAM or Slave) Write Complete (From BRAM or Slave) complete complete UG018_64c_120803 Figure 3-28: Single Cycle Mode (1:1) DSOCM Write V
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R Application Notes and Reference Designs Xilinx provides several application notes and reference designs utilizing the OCM controllers. Design examples include: x Booting the PPC405 from on-chip memory. x Using the dual port feature of the DSOCM in eight, sixteen and thirty-two bit fabric interfaces x A comparison of PLB versus OCM performance using a software example. For Virtex-II Pro the following application notes and reference designs are available from the Xilinx web site at http://support.
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R 182 Chapter 3: PowerPC 405 OCM Controller www.xilinx.com 1-800-255-7778 PowerPC™ 405 Processor Block Reference Guide UG018 (v2.
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R Chapter 4 PowerPC 405 APU Controller This chapter only applies to the PowerPC 405 in the Virtex-4-FX family and covers the following topics: x “FCM Instruction Processing” x “APU Controller Configuration” x “Interface Definition” x “FCM Interface Timing Specification” Note: The Auxiliary Processor Unit (APU) Controller is not available in the Virtex-II Pro family.
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R Chapter 4: PowerPC 405 APU Controller Virtex4 FX PowerPC405 block APU Controller PowerPC405 core Fabric Co-processor Module (FCM) Decode_Stage Instruction Execute_Stage Operands Exe_Unit Result Writeback_Stage FCM_Decode APUC_Decode Resynchronization_Interface Decode FCM_Exe_Unit LoadData load_reg LoadWB_Stage UG018_04_01_040904 Figure 4-1: Pipeline Flow Diagram The APU Controller serves two purposes: It performs clock domain synchronization between the fast PowerPC clock and the slow FCM
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R has a configurable format and is a true extension of the PowerPC instruction set architecture (ISA). Enabling the APU Controller The PowerPC MSR register must be configured before the processor can use the APU controller. Table 4-1 describes the APU controller-related bits in the MSR.
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R Chapter 4: PowerPC 405 APU Controller Blocking Instructions Any non-autonomous instruction that cannot be predictably aborted and later re-issued must be blocking. During execution of a blocking instruction, all interrupts and exceptions to the PowerPC are blocked, so as not to prevent it from completing. This is, for example, true of the UDI_FCM_Write instruction if the source of the data is a FIFO inside the FCM.
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R Table 4-2: APU Op-codes (Continued) Primary Op-code Extended Op-code Description 0b-----001110 Pre-defined FCM Load/Store 0b-111-010-1- FCM integer divide 0b----------- Pre-defined FPU Load/Store 32 (= 0b011111) 0b1----1-111- Pre-defined FPU Load/Store 59 (= 0b111011) 0b----------- Pre-defined PowerPC FPU instructions 62 (= 0b111110) 0b--------1-- Pre-defined FPU Load/Store 63 (= 0b111111) 0b---------- Pre-defined PowerPC FPU instructions 31 (= 0b011111) (= 0b110---)b a.
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R Chapter 4: PowerPC 405 APU Controller Complex Arithmetic Group x fdiv x fdivs x fsqrt x fsqrts x fdiv. x fdivs. x fsqrt. x fsqrts. x fctiwz. x frsqrte. Conversion Group x fcfid x fctidz x fctiw. x fctid x fctiw x fctiwz x fres. x frsqrte Estimates Group x fres The decoded instructions require an FCM floating point unit to be used. FPU instructions that return results to the PowerPC will default to execute as non-autonomous, nonblocking.
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R The extended op-code for Load/Store operations are described in Table 4-3.
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R Chapter 4: PowerPC 405 APU Controller FCM User-Defined Instruction Decoding User-defined instructions that are not recognized (i.e., decoded) by the APU Controller are passed to the FCM for decoding in fabric logic. While this allows for more custom instructions than the eight APU Controller decoded UDIs to be defined, additional instructions come at an execution speed penalty. Decoding in the FCM is not as efficient as in the APU Controller.
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R FCM internal data hazards such as read-after-write (RAW) and write-after-write (WAW) are eliminated if the designer ensures that all FCM instructions complete in order. This can be done conservatively by asserting FCMAPUDONE only after each instruction has completed. This is, however, incompatible with execution pipelining. A pipelined FCM must handle all possible hazards internally.
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R Chapter 4: PowerPC 405 APU Controller Table 4-4: APU Controller Configuration Register Bit Description (Continued) Name Bit Description ForceAlign 20 Force word alignment for FCM Load/Store data. Forces two least significant address bits to 0. LETrap 21 Enable little-endian Traps for FCM Load/Store. If FCM expects big-endian and the accessed memory is little-endian (APUFCMENDIAN=1), an alignment exception will be cast. BETrap 22 Enable big-endian Traps for FCM Load/Store.
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R Table 4-5: UDI Configuration Register Bit Description (Continued) Name Bit Description - (21:25) Hard coded 0b0000. Type (26:27) Instruction class definition, and reserved DCR use: 0b00 = Blocking 0b01 = Non-blocking 0b10 = Autonomous 0b11 = reserved for UDI register selection for DCR read operations (see “DCR Access to the Configuration Registers”).
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R Chapter 4: PowerPC 405 APU Controller APU Controller Input Signals All APU Controller input signals should be synchronized on the FCM clock (CPMFCMCLK). Table 4-6: FCM Interface Input Signals Signal Function FCMAPUINSTRACK Valid instruction decoded in FCM. Must be asserted the first cycle in which FCMAPUDECODEBUSY is low, after APUFCMINSTRVALID has been asserted. All instruction decode signals from the FCM to APU Controller must be valid when asserted.
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R Table 4-6: FCM Interface Input Signals (Continued) Signal Function FCMAPUDCDLDSTWD FCM decoded load/store instruction does word transfer. FCMAPUDCDLDSTDW FCM decoded load/store instruction does double word transfer. FCMAPUDCDLDSTQW FCM decoded load/store instruction does quad word transfer. FCMAPUDCDTRAPLE FCM decoded load/store instruction will cause alignment exception if the storage Endian attribute is 1’b1.
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R Chapter 4: PowerPC 405 APU Controller APU Controller Output Signals All APU Controller output signals are synchronous with the FCM clock (CPMFCMCLK). Table 4-7: FCM Interface Output Signals Signal Function APUFCMINSTRUCTION[0:31] Instruction being presented to the FCM. Is valid as long as APUFCMINSTRVALID is high.
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R APU Controller Attributes The following input signals are used as reset values for the APU Controller configuration registers. The reset values can be over-written using DCR. For details see the “APU Controller Configuration” section in this chapter. Table 4-8: APU Controller Attributes Attribute Signal Function TIEAPUUDI1[0:23] Reset value for UDI register 1. TIEAPUUDI2[0:23] Reset value for UDI register 2. TIEAPUUDI3[0:23] Reset value for UDI register 3.
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R Chapter 4: PowerPC 405 APU Controller Table 4-10: Bit Map Between TIEAPUCONTROL and APU Configuration Register APU Controller Configuration Field 198 TIEAPUCONTROL Bits LdStDecDis 0 UDIDecDis 1 ForceUDINonB 2 FPUDecDis 3 FPUCArithDis 4 FPUConvIDis 5 FPUEstimIDis 6 ForceFPUNonB 7 StoreWBOK 8 LdStPrivOp 9 ForceAlign 10 LETrap 11 BETrap 12 BESteer 13 APUDiv 14 FCMEn 15 www.xilinx.com 1-800-255-7778 PowerPC™ 405 Processor Block Reference Guide UG018 (v2.
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R FCM Interface Timing Specification Autonomous Transactions CPMFCMCLK APUFCMINSTRUCTION APUFCMINSTRVALID APUFCMDECODED APUFCMDECUDI[0:2] APUFCMDECUDIVALID APUFCMRADATA/ APUFCMRBDATA APUFCMOPERANDVALID FCMAPUDONE APUFCMWRITEBACKOK FCMAPUSLEEPNOTREADY UG018_04_02_042304 Figure 4-3: APU Controller Decoded Autonomous Transaction Example Note: Actual timing results may vary from those shown in Figure 4-3.
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R Chapter 4: PowerPC 405 APU Controller CPMFCMCLK APUFCMINSTRUCTION APUFCMINSTRVALID FCMAPUINSTRACK FCMAPUOPTIONS APUFCMRADATA/ APUFCMRBDATA APUFCMOPERANDVALID FCMAPUDONE APUFCMWRITEBACKOK FCMAPUSLEEPNOTREADY UG018_04_03_032504 Figure 4-4: FCM Decoded Autonomous Transaction Example Note: Actual timing results may vary from those shown in Figure 4-4. For example, the operands could come later than shown. 200 www.xilinx.com 1-800-255-7778 PowerPC™ 405 Processor Block Reference Guide UG018 (v2.
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R Blocking Transactions CPMFCMCLK APUFCMINSTRUCTION APUFCMINSTRVALID FCMAPUINSTRACK FCMAPUOPTIONS APUFCMRADATA/ APUFCMRBDATA APUFCMOPERANDVALID FCMAPURESULT FCMAPUDONE/ FCMAPURESULTVALID APUFCMWRITEBACKOK FCMAPUSLEEPNOTREADY UG018_04_04_032504 Figure 4-5: FCM Decoded Blocking Transaction Example Note: Actual timing results may vary from those shown in Figure 4-5. For example, the operands could come later than shown. PowerPC™ 405 Processor Block Reference Guide UG018 (v2.0) August 20, 2004 www.
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R Chapter 4: PowerPC 405 APU Controller Non-Blocking Transactions CPMFCMCLK APUFCMINSTRUCTION APUFCMINSTRVALID APUFCMDECODED APUFCMRADATA/ APUFCMRBDATA APUFCMOPERANDVALID FCMAPURESULT FCMAPUDONE/ FCMAPURESULTVALID APUFCMWRITEBACKOK FCMAPUSLEEPNOTREADY UG018_04_05_032504 Figure 4-6: APU Controller Decoded Non-Blocking Transaction Example Note: Actual timing results may vary from those shown in Figure 4-6. For example, the operands could come later than shown. 202 www.xilinx.
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R FCM Load Instruction CPMFCMCLK APUFCMINSTRUCTION APUFCMINSTRVALID APUFCMDECODED APUFCMLOADDATA APUFCMLOADDVALID FCMAPUDONE APUFCMWRITEBACKOK FCMAPUSLEEPNOTREADY UG018_04_06_042304 Figure 4-7: APU Controller Decoded Load Instruction Example Note: Load data can arrive at the same time as the instruction or at a later clock cycle than shown in Figure 4-7. PowerPC™ 405 Processor Block Reference Guide UG018 (v2.0) August 20, 2004 www.xilinx.
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R Chapter 4: PowerPC 405 APU Controller CPMFCMCLK APUFCMINSTRUCTION APUFCMINSTRVALID APUFCMDECODED APUFCMLOADDATA word0 word1 APUFCMLOADDVALID FCMAPUDONE FCMAPULOADWAIT FCMAPUSLEEPNOTREADY UG018_04_07_042304 Figure 4-8: APU Controller Decoded a Double Word Load Instruction with LoadWait Example Note: Load data can arrive at the same time as the instruction or at a later clock cycle than shown in Figure 4-8. Also, load data might not be sent back-to-back. Users should look at the valid signal.
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R CPMFCMCLK APUFCMINSTRUCTION APUFCMINSTRVALID APUFCMDECODED FCMAPURESULT FCMAPUDONE APUFCMWRITEBACKOK FCMAPUSLEEPNOTREADY UG018_04_09_032504 Figure 4-10: APU Controller Decoded Store Instruction with StoreWBOK=1 FCM Exception CPMFCMCLK APUFCMINSTRUCTION APUFCMINSTRVALID APUFCMRADATA/ APUFCMRBDATA APUFCMOPERANDVALID FCMAPUEXCEPTION APUFCMFLUSH UG018_04_10_032504 Figure 4-11: FCM Exception Note: FCMAPUEXEPTION may be sent at any time during the execution of a non-autonomous instruction.
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R Chapter 4: PowerPC 405 APU Controller FCM Decoding Using Decode Busy Signal CPMFCMCLK APUFCMINSTRUCTION APUFCMINSTRVALID FCMAPUDECODEBUSY FCMAPUOPTIONS FCMAPUINSTRACK UG018_04_11_032504 Figure 4-12: FCM Decode Asserting DecodeBusy CPMFCMCLK APUFCMINSTRUCTION APUFCMINSTRVALID FCMAPUDECODEBUSY FCMAPUOPTIONS FCMAPUINSTRACK UG018_04_12_042304 Figure 4-13: FCM Deasserting DecodeBusy 206 www.xilinx.com 1-800-255-7778 PowerPC™ 405 Processor Block Reference Guide UG018 (v2.
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R Appendix A RISCWatch and RISCTrace Interfaces This appendix summarizes the interface requirements between the PowerPC 405 and the RISCWatch and RISCTrace tools. The requirement for separate JTAG and trace connectors is being replaced with a single Mictor connector to improve the electrical and mechanical characteristics of the interface. Pin assignments for the Mictor connector are included in the signal-mapping tables.
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R Appendix A: RISCWatch and RISCTrace Interfaces Table A-1: JTAG Connector Signals for RISCWatch RISCWatch Pin Description I/O Signal Name 1 Input TDO 2 No Connect Reserved 3 Output TDIa JTAG test-data in. 4 Output TRST JTAG test reset. 5 No Connect Reserved 6 Output +Powerb Processor power OK 7 Output TCKc JTAG test clock.
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R Table A-2: PowerPC 405 to RISCWatch Signal Mapping PowerPC 405 RISCWatch Signal I/O C405JTGTDOa Signal I/O JTAG Mictor Connector Connector Pin Pin Output TDO Input 1 11 JTGC405TDI Input TDI Output 3 19 JTGC405TRSTNEG Input TRST Output 4 21 JTGC405TCK Input TCK Output 7 15 JTGC405TMS Input TMS Output 9 17 DBGC405DEBUGHALTb2 Input HALT Output 11 7 a. This signal must be driven by a tri-state device using C405JTGTDOEN as the enable signal. b.
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R Appendix A: RISCWatch and RISCTrace Interfaces Table A-3: Trace Connector Signals for RISCTrace RISCTrace Pin Description I/O 1 No Connect Reserved 2 No Connect Reserved 3 Output TrcClk 4 No Connect Reserved 5 No Connect Reserved 6 No Connect Reserved 7 No Connect Reserved 8 No Connect Reserved 9 No Connect Reserved 10 No Connect Reserved 11 No Connect Reserved 12 Output TS1O Execution status. 13 Output TS2O Execution status.
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R Table A-4: PowerPC 405 to RISCTrace Signal Mapping PowerPC 405 I/O Signal I/O Trace Connector Pin C405TRCCYCLE Output TrcClk Input 3 6 C405TRCODDEXECUTIONSTATUS[0] Output TS1O Input 12 24 C405TRCODDEXECUTIONSTATUS[1] Output TS2O Input 13 26 C405TRCEVENEXECUTIONSTATUS[0] Output TS1E Input 14 28 C405TRCEVENEXECUTIONSTATUS[1] Output TS2E Input 15 30 C405TRCTRACESTATUS[0] Output TS3 Input 16 32 C405TRCTRACESTATUS[1] Output TS4 Input 17 34 C405TRCTRACESTATUS[2]
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R 212 Appendix A: RISCWatch and RISCTrace Interfaces www.xilinx.com 1-800-255-7778 PowerPC™ 405 Processor Block Reference Guide UG018 (v2.
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R Appendix B Signal Summary Interface Signals Table B-1 lists the PowerPC 405 interface signals in alphabetical order. A cross reference is provided to each signal description. The signal naming conventions used are described in “Signal Naming Conventions” in Chapter 2. Table B-1: PowerPC 405 Interface Signals in Alphabetical Order Signal FPGA Typea I/O If Unused Interface Function Type Ties To:b APUFCMDECODED V-4 O FCM No Connect Indicates APU Controller decoded FCM instruction.
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R Table B-1: Appendix B: Signal Summary PowerPC 405 Interface Signals in Alphabetical Order (Continued) Signal FPGA Typea I/O If Unused Function Interface Type Ties To:b APUFCMXERCA V-4 O FCM No Connect Reflects the XerCA bit used for extended arithmetic. BRAMDSOCMCLK V-II Pro and V-4 I DSOCM 1 Clocks the DSOCM controller and the data side interface logic BRAMDSOCMRDDBUS[0:31] V-II Pro and V-4 I DSOCM 0 Read data bus from the FPGA fabric to the DSOCM controller.
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R Table B-1: PowerPC 405 Interface Signals in Alphabetical Order (Continued) Signal FPGA Typea I/O If Unused Function Interface Type Ties To:b C405JTGCAPTUREDR (OUTPUT) V-II Pro and V-4 O JTAG No Connect Indicates the TAP controller is in the capture-DR state. C405JTGEXTEST (OUTPUT) V-II Pro and V-4 O JTAG No Connect Indicates the JTAG EXTEST instruction is selected.
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R Table B-1: Appendix B: Signal Summary PowerPC 405 Interface Signals in Alphabetical Order (Continued) Signal FPGA Typea I/O If Unused Function Interface Type Ties To:b C405PLBICUABUS[0:29] V-II Pro and V-4 O ISPLB No Connect Specifies the memory address of the instruction-fetch request. Bits 30:31 of the 32-bit address are assumed to be zero. C405PLBICUCACHEABLE V-II Pro and V-4 O ISPLB No Connect Indicates the value of the cacheability storage attribute for the target address.
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R Table B-1: PowerPC 405 Interface Signals in Alphabetical Order (Continued) Signal FPGA Typea I/O If Unused Function Interface Type Ties To:b CPMC405TIMERCLKEN V-II Pro and V-4 I CPM 1 Enables the timer clock zone. CPMC405TIMERTICK V-II Pro and V-4 I CPM 1 Increments or decrements the PowerPC 405 timers every time it is active with the CPMC405CLOCK. CPMDCRCLK V-4 I CPM 1 DCR bus interface clock for PPC405 synchronization.
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R Table B-1: Appendix B: Signal Summary PowerPC 405 Interface Signals in Alphabetical Order (Continued) Signal FPGA Typea I/O If Unused Function Interface Type Ties To:b EICC405EXTINPUTIRQ V-II Pro and V-4 I EIC 0 Indicates an external noncritical interrupt occurred. FCMAPUCR[0:3] V-4 I FCM 0 Condition result bits to set in the PowerPC CR field FCMAPUDCDCREN V-4 I FCM 0 FCM decoded instruction sets condition register (CR) bits.
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R Table B-1: PowerPC 405 Interface Signals in Alphabetical Order (Continued) Signal FPGA Typea I/O If Unused Function Interface Type Ties To:b FCMAPUDONE V-4 I FCM 0 Indicates the completion of the instruction in the FCM to the APU Controller FCMAPUEXCEPTION V-4 I FCM 0 FCM generate program exception on the processor (vector 0x0700). FCMAPUEXEBLOCKINGMCO V-4 I FCM 0 FCM decoded multi cycle operation of blocking class.
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R Table B-1: Appendix B: Signal Summary PowerPC 405 Interface Signals in Alphabetical Order (Continued) Signal FPGA Typea I/O If Unused Function Interface Type Ties To:b ISOCMDCRBRAMRDSELECT V-4 O ISOCM No Connect Select between even and odd instruction words from DCR access JTGC405BNDSCANTDO (INPUT) V-II Pro and V-4 I JTAG 0 JTAG boundary scan input from the previous boundary scan element TDO output. JTGC405TCK (INPUT) V-II Pro and V-4 I JTAG 1 JTAG TCK (test clock).
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R Table B-1: PowerPC 405 Interface Signals in Alphabetical Order (Continued) Signal FPGA Typea I/O If Unused Function Interface Type Ties To:b PLBC405DCUWRDACK (INPUT) V-II Pro and V-4 I DSPLB 0 Indicates the data on the DCU writedata bus is being accepted by the PLB slave. PLBC405ICUADDRACK (INPUT) V-II Pro and V-4 I ISPLB 0 Indicates a PLB slave acknowledges the current ICU fetch request.
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R Table B-1: Appendix B: Signal Summary PowerPC 405 Interface Signals in Alphabetical Order (Continued) Signal FPGA Typea I/O If Unused Function Interface Type Ties To:b TIEC405DETERMINISTICMULT (INPUT) V-II Pro and V-4 I Control 0 Specifies whether all multiply Required operations complete in a fixed number of cycles or have an early-out capability.
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R Appendix C Processor Block Timing Model This section explains all of the timing parameters associated with the IBM PPC405 Processor Block. It is intended to be used in conjunction with Module 3 of the Virtex-II Pro or Virtex-4 Data Sheet and the Timing Analyzer (TRCE) report from Xilinx software. For specific timing parameter values and clocking considerations, refer to the appropriate data sheet(s).
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R Appendix C: Processor Block Timing Model PowerPC miscellaneous (PPC), Trace Port (TRC), JTAG, Instruction-Side On-Chip Memory (ISOCM), and Data-Side On-Chip Memory (DSOCM), Auxiliary Processor Unit Controller (APU, Virtex-4 only), and Fabric Coprocessor Module (FCM, Virtex-4 only). Table C-1 associates five clocks (Virtex-II Pro) or seven clocks (Virtex-4) with their corresponding interface blocks. All signal parameters discussed in this section are characterized at a rising clock edge.
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R Table C-2: Parameters Relative to the Core Clock (CPMC405CLOCK) Parameter Function Signals Setup/Hold: TPCCK_DCR/TPCKC_DCRa Control Inputs DCRC405ACK TPDCK_DCR/TPCKD_DCRa Data Inputs DCRC405DBUSIN[0:31] TPCCK_CPM/TPCKC_CPM Control Inputs CPMC405TIMERTICK CPMC405CPUCLKEN CPMC405TIMERCLKEN CPMC405JTAGCLKEN TPCCK_RST/TPCKC_RST Control Inputs RSTC405RESETCHIP RSTC405RESETCORE RSTC405RESETSYS TPCCK_DBG/TPCKC_DBG Control Inputs DBGC405DEBUGHALT DBGC405UNCONDDEBUGEVENT TPCCK_TRC/TPCKC_TRC Con
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R Appendix C: Processor Block Timing Model Table C-2: Parameters Relative to the Core Clock (CPMC405CLOCK) (Continued) Parameter Function Signals Clock: TCPWH Clock Pulse Width, High State CPMC405CLOCK TCPWL Clock Pulse Width, Low State CPMC405CLOCK a. Virtex-II Pro only. See Table C-3 for Virtex-4 DCR bus timing parameters. 226 www.xilinx.com 1-800-255-7778 PowerPC™ 405 Processor Block Reference Guide UG018 (v2.
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R Table C-3: Parameters Relative to the DCR Bus Clock (CPMDCRCLK, Virtex-4 Only) Parameter Function Signals Setup/Hold: TPPCDCK_EXDCRACK TPPCCKD_EXDCRACK Control Inputs EXTDCRC405ACK TPPCDCK_EXDCRDBUS TPPCCKD_EXCDRDBUS Data Inputs EXTDCRC405DBUSIN[0:31] Control Outputs EXTDCRREAD Clock to Out: TPPCCKO_EXDCRRD TPPCCKO_EXDCRWR EXTDCRWRITE TPPCCKO_EXDCRABUS Address Outputs EXTDCRABUS[0:9] TPPCCKO_EXDCRDBUSO Data Outputs EXTDCRDBUSOUT[0:31] TDCRPWH Clock Pulse Width, High State CPMDCRCLK
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R Appendix C: Processor Block Timing Model Table C-4: Parameters Relative to the FCM Clock (CPMFCMCLK, Virtex-4 Only) Parameter Function Signals Setup/Hold: TPCCK_FCM/TPCKC_FCM Control Inputs FCMAPUINSTRACK FCMAPUDONE FCMAPUSLEEPNOTREADY FCMAPUDECODEBUSY FCMAPUDCDGPRWRITE FCMAPUDCDRAEN FCMAPUDCDRBEN FCMAPUDCDPRIVOP FCMAPUDCDFORCEALIGN FCMAPUDCDXEROVEN FCMAPUDCDXERCAEN FCMAPUDCDCREN FCMAPUEXECRFIELD[0:2] FCMAPUDCDLOAD FCMAPUDCDSTORE FCMAPUDCDUPDATE FCMAPUDCDLDSTBYTE FCMAPUDCDLDSTHW FCMAPUDCDLDSTWD FCM
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R Table C-4: Parameters Relative to the FCM Clock (CPMFCMCLK, Virtex-4 Only) (Continued) Parameter TPCKDO_FCM Function Signals Data Outputs APUFCMINSTRUCTION[0:31] APUFCMRADATA[0:31] APUFCMRBDATA[0:31] APUFCMLOADDATA[0:31] Clock High Width Clock Low Width CPMFCMCLK Clock: Tfcmpwh and TFCMPWL Table C-5: Parameters Relative to the PLB Clock (PLBCLK) Parameter Function Signals Setup/Hold: TPCCK_PLB/TPCKC_PLB Control inputs PLBC405DCUADDRACK PLBC405DCUBUSY PLBC405DCUERR PLBC405DCURDDACK PLBC405DCU
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R Appendix C: Processor Block Timing Model Table C-5: Parameters Relative to the PLB Clock (PLBCLK) (Continued) Parameter Function Signals TPCKDO_PLB Data outputs C405PLBDCUWRDBUS[0:63] TPCKAO_PLB Address outputs C405PLBDCUABUS[0:31] C405PLBICUABUS[0:29] TPPWH Clock pulse width, High state PLBCLK TPPWL Clock pulse width, Low state PLBCLK Clock: Table C-6: Parameters Relative to the JTAG Clock (JTAGC405TCK) Parameter Function Signals Setup/Hold: TPCCK_JTAG/TPCKC_JTAG Control inputs JTG
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R Table C-7: Parameters Relative to the ISOCM Clock (BRAMISOCMCLK) (Continued) Parameter Function Signals Clock to Out: TPCKCO_ISOCM Control outputs ISOCMBRAMEN ISOCMBRAMODDWRITEEN ISOCMBRAMEVENWRITEEN ISOCMDCRBRAMEVENEN (Virtex-4 only) ISOCMDCRBRAMODDEN (Virtex-4 only) ISOCMDCRBRAMRDSELECT (Virtex-4 only) TPCKAO_ISOCM Address outputs ISOCMBRAMRDABUS[8:28] ISOCMBRAMWRABUS[8:28] TPCKDO_ISOCM Data outputs ISOCMBRAMWRDBUS[0:31] TIPWH Clock pulse width, High state BRAMISOCMCLK TIPWL Clock pulse
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R Appendix C: Processor Block Timing Model 1 2 Tx PWL Tx PWH CLOCK TPCCK TPCKC CONTROL INPUTS TPCKCO CONTROL OUTPUTS TPCKDO DATA OUTPUTS TPDCK TPCKD DATA INPUTS TPCKAO ADDRESS OUTPUTS UG012_C1_02_121701 Figure C-2: Processor Block Timing Relative to Clock Edge 232 www.xilinx.com 1-800-255-7778 PowerPC™ 405 Processor Block Reference Guide UG018 (v2.
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Index A abort data-side PLB 78, 97 instruction-side PLB 54, 67 address acknowledge data-side PLB 80 instruction-side PLB 55 address bus data-side PLB 74 DCR 105 instruction-side PLB 52 address pipelining cacheable fetch 62, 63 cacheable reads 86 data 71 fetch requests 49 non-cacheable fetch 65 PPC405 37 clock and power management See CPM interface. core-configuration register See CCR0. CPM interface 35 signals 36 CPU control interface 41 CR 25 critical interrupt request 111 D B data-cache unit See DCU.
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R cacheable 49 non-cacheable request size 48 prefetching 49 without allocate 49 FIT description of 29 timer exception 39 update frequency 38 fixed-interval timer See FIT. G general-purpose register See GPR.
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R instruction-side PLB interface 50 JTAG interface 111 naming conventions 34 processor reset See core reset. programmable-interval timer See PIT.
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R 236 www.xilinx.com 1-800-255-7778 PowerPC™ 405 Processor Block Reference Guide UG018 (v2.