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116 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 4: MicroBlaze Instruction Set Architecture
R
msrclr
Read MSR and clear bits in MSR
Description
Copies the contents of the special purpose register MSR into register rD.
Bit positions in the IMM value that are 1 are cleared in the MSR. Bit positions that are 0 in
the IMM value are left untouched.
Pseudocode
(rD) ← (MSR)
(MSR)
← (MSR) ∧ (IMM))
Registers Altered
• rD
• MSR
Latency
1 cycle
Note
MSRCLR will affect some MSR bits immediately (e.g. Carry) while the remaining bits will
take effect one cycle after the instruction has been executed.
The immediate values has to be less than 2
14
. Only bits 18 to 31 of the MSR can be cleared.
msrclr rD, Imm
1 0 0 1 0 1 rD 0 0 0 0 1 0 0 Imm14
0 6 11 16 17 18 31