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142 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 4: MicroBlaze Instruction Set Architecture
R
sw
Store Word
Description
Storesthe contentsof register rD, into the word alignedmemory locationthat resultsfrom
adding the contents of registers rA and rB.
Pseudocode
Addr ← (rA) + (rB)
Addr[30:31]
← 00
Mem(Addr)
← (rD)[0:31]
Registers Altered
• ESR [S]
Latency
1 cycle
sw rD, rA, rB
1 1 0 1 1 0 rD rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21 31