Inc. Typewriter User Manual

22 www.xilinx.com MicroBlaze Processor Reference Guide

1-800-255-7778 UG081 (v6.0) June 1, 2006

Chapter 1: MicroBlaze Architecture

Machine Status Register (MSR)

The Machine Status Register contains control and status bits for the processor. It can be

read with an MFS instruction. When reading the MSR, bit 29 is replicated in bit 0 as the

carry copy. MSR can be written using either an MTS instruction or the dedicated MSRSET

and MSRCLR instructions.

Whenwritingto the MSR, someofthebitswilltakeseffectimmediately(e.gCarry)andthe

remaining bits take effect one clock cycle later. Any value written to bit 0 is discarded.

When used with an MTS or MFS instruction the MSR is speciﬁed by setting Sx = 0x0001.

0 31

↑

Figure 1-3: PC

Table 1-8: Program Counter (PC)

Bits Name Description Reset Value

0:31 PC

Program Counter

Address of executing instruction,

i.e. “mfs r20” will store the address

of the mfs instruction itself in R2

0x00000000

0 21 22 23 24 25 26 27 28 29 30 31

↑ ↑ ↑↑↑ ↑ ↑↑↑↑↑↑↑

CC RESERVED PVR EIP EE DCE DZ ICE FSL BIP C IE BE

Figure 1-4: MSR

Table 1-9: Machine Status Register (MSR)

Bits Name Description Reset Value

0CC

Arithmetic Carry Copy

Copy of theArithmetic Carry(bit 29).

CC is always the same as bit C.

1:20 Reserved

21 PVR

Processor Version Register exists

0 No Processor Version Register

1 Processor Version Register exists

Read only

Based on

option

C_PVR