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26 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 1: MicroBlaze Architecture
R
Branch Target Register (BTR)
The Branch Target Register only exists if the MicroBlaze processor is configured to use
exceptions. The register stores the branch target address for all delay slot branch
instructions executed while MSR[EIP] = 0. If an exception is caused by an instruction in a
delay slot (i.e. ESR[DS]=1) then the exception handler should return execution to the
address stored in BTR instead of the normal exception return address stored in r17. When
read with the MFS instruction the BTR is specified by setting Sa = 0x000B.
Table 1-12: Exception Specific Status (ESS)
Exception
Cause
Bits Name Description Reset Value
Unaligned
DataAccess
20 W
Word Access Exception
0 unaligned halfword access
1 unaligned word access
0
21 S Store Access Exception
0 unaligned load access
1 unaligned store access
0
22:26 Rx
Source/Destination Register
General purpose register used
as source(Store) or destination
(Load) in unaligned access
0
Illegal
Instruction
20:26 Reserved 0
Instruction
bus error
20:26 Reserved 0
Data bus
error
20:26 Reserved 0
Divide by
zero
20:26 Reserved 0
Floating
point unit
20:26 Reserved 0
0 31
↑
BTR
Figure 1-7: BTR