Inc. Typewriter User Manual

MicroBlaze Processor Reference Guide www.xilinx.com 59
UG081 (v6.0) June 1, 2006 1-800-255-7778
Debug Interface Description
R
0b01=byte1 or halfword0, 0x10=byte2, and 0x11=byte3 or halfword1. The selection of
half-word or byte access is based on the control bit for the data word in step 4.
3. If DCACHE_FSL_OUT_Full = 1 then stall until it goes low
4. Write the data to be stored to DCACHE_FSL_OUT_Data. For byte and halfword
accesses the data is mirrored accordingly onto byte-lanes. The control bit should be
low (DCACHE_FSL_OUT_Control = 0) for a word or halfword access, and high for a
byte access.
Debug Interface Description
The debug interface on MicroBlaze is designed to work with the Xilinx Microprocessor
Debug Module (MDM) IP core. The MDM is controlled by the Xilinx Microprocessor
Debugger (XMD) through the JTAG port of the FPGA. The MDM can control multiple
MicroBlaze processors at the same time. The debug signals on MicroBlaze are listed in
Table 2-9.
Trace Interface Description
The MicroBlaze core exports a number of internal signals for trace purposes. This signal
interface is not standardized and new revisions of the processor may not be backward
compatible for signal selection or functionality. Users are recommended not to design
custom logic for these signals, but rather to use them via Xilinx provided analysis IP. The
current set of trace signals were last updated for MicroBlaze v5.00.a and are listed in
Table 2-10.
Table 2-9: MicroBlaze Debug signals
Signal Name Description VHDL Type Direction
Dbg_Clk JTAG clock from MDM std_logic input
Dbg_TDI JTAG TDI from MDM std_logic input
Dbg_TDO JTAG TDO to MDM std_logic output
Dbg_Reg_En Debug register enable from
MDM
std_logic input
Dbg_Capture JTAG BSCAN capture signal
from MDM
std_logic input
Dbg_Update JTAG BSCAN update signal
from MDM
std_logic input
Table 2-10: MicroBlaze Trace signals
Signal Name Description VHDL Type Direction
Trace_Valid_Instr Valid instruction on trace
port.
std_logic output
Trace_Instruction
1
Instruction code std_logic_vector
(0 to 31)
output
Trace_PC
1
Program counter std_logic_vector
(0 to 31)
output