Inc. Typewriter User Manual

74 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 4: MicroBlaze Instruction Set Architecture
R
addi
Arithmetic Add Immediate
Description
The sum ofthe contents ofregistersrA and thevaluein theIMMfield, sign-extendedto32
bits, is placed into register rD. Bit 3 of the instruction (labeled as K in the figure) is set to a
one for the mnemonic addik. Bit 4 of the instruction (labeled as C in the figure) is set to a
one for the mnemonic addic. Both bits are set to a one for the mnemonic addikc.
When an addiinstructionhas bit3 set(addik, addikc), thecarry flag willKeep its previous
value regardlessof the outcome of the executionof the instruction. If bit 3 is cleared (addi,
addic), then the carry flag will be affected by the execution of the instruction.
When bit 4 of the instruction is set to a one (addic, addikc), the content of the carry flag
(MSR[C]) affects the execution of the instruction. When bit 4 is cleared (addi, addik), the
contentofthecarryflag doesnotaffecttheexecution oftheinstruction(providinganormal
addition).
Pseudocode
if C = 0 then
(rD) ← (rA) + sext(IMM)
else
(rD) ← (rA) + sext(IMM) + MSR[C]
if K = 0 then
MSR[C] ← CarryOut
Registers Altered
• rD
• MSR[C]
Latency
1 cycle
Notes
The C bit in the instruction opcode is not the same as the carry bit in the MSR.
By default, Type BInstructionswill take the16-bit IMM fieldvalue and sign extendit to 32
bits to use as the immediate operand. This behavior can be overridden by preceding the
Type B instruction with an imm instruction. See the imm instruction for details on using
32-bit immediate values.
addi
rD, rA, IMM Add Immediate
addic
rD, rA, IMM Add Immediate with Carry
addik
rD, rA, IMM Add Immediate and Keep Carry
addikc
rD, rA, IMM Add Immediate with Carry and Keep Carry
0 0 1 K C 0 rD rA IMM
0 6 11 16 31