Service manual
RX-V363/HTR-6130
50
RX-V363/HTR-6130
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
ROUT3
NC
LOUT2
NC
ROUT2
NC
LOUT1
NC
ROUT1
NC
LIN
RIN
VCOM
VREFH
AVDD
AVSS
RX0
NC
RX1
TEST1
RX2
NC
RX3
PVSS
R
PVDD
RX4
TEST2
RX5
CAD0
RX6
CAD1
RX7
I2C
DAUX2
VIN
MCLK
TX0
TX1
INT0
O
–
O
–
O
–
O
–
O
–
I
I
–
–
–
–
I
–
I
I
I
–
I
–
–
–
I
I
I
I
I
I
I
I
I
I
I
O
O
O
DAC3 R ch analog output pin
No connect pin
No internal bonding / This pin should be opened
DAC2 L ch analog output pin
No connect pin
No internal bonding / This pin should be opened
DAC2 R ch analog output pin
No connect pin
No internal bonding / This pin should be opened
DAC1 L ch analog output pin
No connect pin
No internal bonding / This pin should be opened
DAC1 R ch analog output pin
No connect pin
No internal bonding / This pin should be opened
L ch analog input pin
R ch analog input pin
Common voltage output pin
2.2 F capacitor should be connected to AVSS externally
Positive voltage reference input pin, AVDD
Analog power supply pin, 4.5 V to 4.5 V
Analog ground pin, 0 V
Receiver channel 0 pin (Internal biased pin / Internally biased at PVDD/2)
No connect pin
No internal bonding / This pin should be connected to PVSS
Receiver channel 1 pin (Internal biased pin / Internally biased at PVDD/2)
Test 1 pin
This pin should be connected to PVSS
Receiver channel 2 pin (Internal biased pin / Internally biased at PVDD/2)
No connect pin
No internal bonding / This pin should be connected to PVSS
Receiver channel 3 pin (Internal biased pin / Internally biased at PVDD/2)
PLL ground pin
External resistor pin
12 k-ohms +/-1 % resistor should be connected to PVSS externally
PLL power supply pin, 4.5 V to 4.5 V
Receiver channel 4 pin (Internal biased pin / Internally biased at PVDD/2)
Test 2 pin
This pin should be connected to PVSS
Receiver channel 5 pin (Internal biased pin / Internally biased at PVDD/2)
Chip address 0 pin (ADC/DAC part)
Receiver channel 6 pin (Internal biased pin / Internally biased at PVDD/2)
Chip address 1 pin (ADC/DAC part)
Receiver channel 7 pin (Internal biased pin / Internally biased at PVDD/2)
Control mode select pin
“L”: 4-wire serial, “H”: I2C bus
Auxiliary audio data input pin (DIR/DIT part)
V-bit input pin for transmitter output
Master clock input pin
Transmit channel (through data) output 0 pin
Transmit channel output 1 pin
When TX bit = “0”, transmit channel (through data) output 1 pin.
When TX bit = “1”, transmit channel (DAUX2 data) output pin (default)
Interrupt 0 pin
Pin No. Function Name I/O Detail of Function
Note: All input pins except internal biased pins and internal pull-down pin should not be left floating.