Service manual

[1]
[2]
[3]
[4]
[5]
[6]
[7]
Register
Decoder
RAM
CPU
DSP5
WC SEL & SYNC DETECTOR
Decoder
Register
DIR2
44.1K
48K
DIR2 2
[8]
Data Bus
Address Bus
SLOT NO.
FPGA
MASTER
CLOCK
48V
/CS1
/CON1
I11
I12
[75 ]
LOCK
WC
/CS2
/CON2
I21
I22
/CS3
/CON3
I31
I32
/CS4
/CON4
I41
I42
/CS5
/CON5
I51
I52
/CS6
/CON6
I61
I62
/CS7
/CON7
I71
I72
/CS8
/CON8
I81
I82
[INPUT UNIT ID]
[PHANTOM MASTER]
[+48V]
[CONTROL PORT]
[A]
[B]
[C]
[WORD CLOCK]
[IN]
[OUT]
[OUTPUT]
[A]
[B]
[C]
WCIC
ID I/O
WCO
DOC
Driver
Receiver
WCO
WCID
[ON]
[OFF]
48V
[ON]
[OFF]
DIR2
DIR2
DIR2
DIR2
IC601
IC307
IC202
IC301
IC302
IC401
IC402
IC404
IC405
IC203
FLASH
IC201
IC101
MB1
IFC2
IPC3
IPC1
WCIB
ID I/O
WCO
DOB
Driver
Receiver
IPC1
WCIA
ID I/O
WCO
DOA
Driver
Receiver
IPC1
LED1
UNC
KEC-92520
1
AI8
6
BLOCK DIAGRAM