Service manual
CDX-497/CDX-397
15
■ IC DATA
IC21 : TC94A54 (MAIN P.C.B)
DSP
* No replacement part available.
I
3AI/F
–
O
3AI/F
O
3AI/F
O
3AI/F
O
3AI/F
I
3AI/F
–
O
3AI/F
O
3AI/F
O
3AI/F
O
3AI/F
O
3AI/F
O
3I/F
O
3I/F
O
3I/F
O
3I/F
O
3I/F
I/O
3I/F
–
–
–
I
3AI/F
O
3AI/F
–
–
O
3AI/F
–
O
O
3AI/F
–
–
–
I/O
To be connected to the RFRP via
0.033 uF.
–
–
Monitor pin for various signals.
To be connected to the TEI via
0.033 uF.
–
–
–
Connected to the VRO and
PVREF within the IC.
To be connected 0.1 uF.
PWM ternary output (AVDD3,
GND, and VREF).
“H” at S1 when Subcode Sync is
detected.
–
–
7.35kHz (At this pin, flags in the
DSP and PLL-circuit clock can be
monitored, using microcontroller
commands. The pin also outputs
text data serially.)
Valid also for 1-bit DAC external
inputs.
General-purpose I/O (input after a
reset).
–
–
–
–
Input to the internal MCK.
–
–
No capacitor is required at the
DVR pin unless the built-in 1-bit
DAC is used.
3.3V must be applied across the
DVDD3 and DVSS3 pins, how-
ever.
–
–
–
IC21 : TC94A54 (MAIN P.C.B)
DSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
RFZI
AVSS3
RFRP
FEI
SBAD/RFDC
TEI
TEZI
AVDD3
FOO
TRO
VREF
FMO
DMO
SBSY
(SPCK)
SBOK
(FOK)
(CLCK)
(MBOV)
IPF
(SPDA)
SFSY
(EMPH)
(LOCK)
(MONIT)
ZDET
(DATA)
(COFS)
GPIN
VSS1
VDD1
XVSS3
XI
XO
XVDD3
DVSS3
RO
DVDD3
DVR
LO
DVSS3
VSS3
VDD3
Input pin for the RF ripple zero-cross signal.
Grounding pin for 3.3V analog circuits.
RF ripple signal output pin.
Focus error signal input pin.
Subbeam addition signal input pin.
Tracking error signal input pin.
Input pin for tracking error signal zero-cross.
Supply voltage pin for 3.3V analog circuit.
Forcus equalizer output pin.
Tracking equalizer output pin.
Analog reference supply voltage pin.
Speed error/feed equalizer output pin.
Disc equalizer output pin.
Pin for outputting the subcode block sync signal. It is “H” at
position S1 when the subcode sync signal is detected.
(CD Processor Status Read Clock (176.4 kHz) output)
Pin for outputting the CRCC check result of a subcode Q data
check. It is “H” when the check result is OK.
(Focus OK signal)
(Input/output pin for the clock used in reading the subcode P
to W data.)
(CD Buffer memory overflow output)
Correction flag output pin.
“H” if the AOUT pin outputs an uncorrectable symbol in C2
correction.
(CD Processor Status signal output)
Pin for outputting the playback frame sync signal.
(Emphasis fiag output pin. ENPH on: “H”. EMPH off: “L”. The
output polarity can be switched, using a command.)
(LOCk signal)
(Pin for monitoring signals in the DSP.)
Output pin for zero detection flag for the 1-bit DAC.
(Pin for outputting subcode P to W data)
(Error Correstion Frame Clock 7.35 kHz output)
General-purpose I/O (DSP)
1.5V grounding pin dedicated to the Digital circuit.
1.5V supply voltage pin dedicated to the Digital circuit.
Grounding pin for the system clock oscillation circuit.
Input pin for the system clock oscillation circuit.
Output pin for the system clock oscillation circuit.
3.3V supply voltage pin for the system clock oscillation circuit.
Grounding pin for the 1-bit DAC.
Output pin for normal R-channel data for the 1-bit DAC.
3.3V supply voltage pin for the 1-bit DAC.
Reference voltage pin for the 1-bit DAC.
Output pin for normal L-channel data for the 1-bit DAC.
Grounding pin for the 1-bit DAC.
3.3V grounding pin dedicated to the I/F circuit
3.3V supply voltage pin dedicated to the I/F circuit.
Pin No. Pin name Description Remark
12345678910111213141516171819202122232425
75747372717069686766656463626160595857565554535251
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
FTE
TNI
TPI
FPI1
FPI2
PNI1
PNI2
RVSS3
MDI
LDO
RVDD3
PNSEL
RFO
99
98
97
96
95
94
93
92
91
90
89
88
DVSS3
RO
CLOCK
GEN
PWM
ADRRESS CIRCUIT
CORRECTION
CIRCUIT
1-bit
DAC
SUBCODE
DEMOCULA
TION
CDRCUIT
ANA
LPF
CPU
I/F
PULL-UP
16k
RAM
DIGITAL
OUT
AUDIO
OUT
PLL
TMAX
AWRC
VCO
RFRP
RFEQ
VRO
AGC
RFDC
RF
FE
TE
10-bit
SAR ADC
5-bit
R-2R DAC
SERVO
CONTROL
DIGITAL EQ
AUTO ADJ
ROM
CAV SERVO
SYNC SIGNAL PROTECTION
EFM DEMODULATION
CLV SERVO
RAN
APC
RF
BLOCK
EFM SLICE
DVDD3
DVR
LO
DVSS3
VSS3
VDD3
VDDM
VSS1S
BUS0
BUS2
BUS3
BUS1
BUCK
/CCE
/RST
STBY
VDDT
FGIN
IO0
IO1
TESTD
VSSP
VCOI
VDDP
TESTC
PIO0
PIO1
PIO2
PIO3
DOUT
AOUT
BCKO
LRCKO
AIN
BCKI
LRCKI
VDD1S
VSS1S
AWRC
PVDD3
PDO
TMAX
LPPN
LPFO
PVREF
VCOF
VCOREF
PVSS3
XVDD3
XO
XI
XVSS3
VDD1
VSS1S
GPIN
ZDET
SFSY
IPF
SBSY
SBOK
DMO
PMO
VREF
TRO
FOO
AVDD3
TEZI
TEI
SBAD/RFDC
FEI
RFRP
AVSS3
RFZI
87
86
85
84
83
82
81
80
79
78
77
76