User Manual
Table Of Contents
- Copyright
- About Audinate
- Introduction
- Installing Dante Controller
- Dante Basics
- Discovery and auto-configuration
- Device Channels
- Differentiating between input and output channels
- Device Names and Channel Labels
- Routing Audio
- Clock Synchronization
- Latency
- Device Lock
- Dante Control and Monitoring
- Starting Dante Controller
- Using Dante Controller
- Network View
- Status Bar
- Network View Tabs
- Channel Groups
- Clock Status Monitoring
- Clock Status Monitor
- Automatic Notification of Device Errors
- Device View
- Device View Tabs
- Multicast Transmit Flow Configuration
- Using Dante Controller with Dante Domain Manager
- Presets
- Troubleshooting
- Fanout
- Messages on Startup
- Computer Configuration Checklist
- Troubleshooting Dante IP Address Configuration
- Troubleshooting Switch Configuration and Cabling
- Index
Dante Controller User Guide
Copyright © 2018 Audinate Pty Ltd. All rights reserved.
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Dante Controller will then resume monitoring (unless the Clock Status Monitoring button is switched off).
To save the event log as an xml file, click Save.
History
The History tab can be used to establish the stability of device clocks. It shows a histogram of clock
frequency offset for the selected device, and the current frequency offset value, updated in real time.
The following information is also displayed:
n Mute status
n Sync status
n External word clock
n Preferred Master status
About Clock Offset
Hardware clocks are based on a vibrating (piezoelectric) quartz crystal. All crystals are slightly different,
and vibrate at slightly different frequencies. When a device ('slave') clock wants to sync to a master
network clock, its frequency must be 'pulled' up or down to match the frequency of the master clock. The
amount that the clock's frequency is pulled is referred to as 'offset'.
Hardware clocks can only support a certain amount of offset, referred to as 'pull range'. If the pull range is
exceeded, the slave clock will lose sync with the master clock, and the device will be automatically muted.
Software clocks typically use an algorithm to derive a clock from an internal counter. Software clocks can
support any amount of offset.
Rapidly-changing offset can also cause a slave clock to lose sync with the master clock.
Various factors can destabilise slave clocks by affecting their offset, such as:
n Overloaded network links
n Poorly-implemented EEE (Energy EfficientEthernet)
n A master clock that is derived from an inaccurate external word clock (one that does not run at its
nominal frequency)
About the Histogram
The horizontal axis of the histogram shows the distribution of clock frequency offset measurements
against the nominal frequency of the clock, in parts per million (ppm). The zero point of the horizontal axis
corresponds to the clock's nominal frequency (i.e. the frequency that the clock is intended to run at - for
example, 98kHz).
The vertical axis shows the number of measurements recorded at each data point, on a logarithmic scale.