Service manual
LSI PIN DESCRIPTION
19
PIN
NO.
I/O FUNCTIONNAME
PIN
NO.
I/O FUNCTIONNAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DAUX
HDLT
DOUT
VFL
OPT
SYNC
MCC
WC
MCB
MCA
SKSY
XI
XO
P256
LOCK
Vss
TC
DIM1
DIM0
DOM1
DOM0
KM1
I
O
O
O
O
O
O
O
O
O
I
I
O
O
O
O
I
I
I
I
I
Auxiliary input for audio data
Asynchronous buffer operation flag
Audio data output
Parity flag output
Fs x 1 Synchronous output signal for DAC
Fs x 1 Synchronous output signal for DSP
Fs x 64 Bit clock output
Fs x 1 Word clock output
Fs x 128 Bit clock output
Fs x 256 Bit clock output
Clock synchronization control input
Crystal oscillator connection or external
clock input
Crystal oscillator connection
VCO oscillating clock connection
PLL lock flag
Logic section power (GND)
PLL time constant switching output
Data input mode selection
Data input mode selection
Data output mode selection
Data output mode selection
Clock mode switching input 1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
RSTN
Vdda
CTLN
PCO
(NC)
CTLP
Vssa
TSTN
KM2
KM0
FS1
FS0
CSM
EXTW
DDIN
LR
Vdd
ERR
EMP
CD0
CCK
CLD
I
I
O
I
I
I
I
O
O
I
I
I
O
O
O
O
I
I
System reset input
VCO section power (+5 V)
VCO control input N
PLL phase comparison output
VCO control input P
VCO section power (GND)
Test terminal. Open for normal use
Clock mode switching input 2
Clock mode switching input 0
Channel status sampling frequency
display output 1
Channel status sampling frequency
display output 0
Channel status output method selection
External synchronous auxiliary input
word clock
EIAJ (AES/EBU) data input
PLL word clock output
Logic section power (+5 V)
Data error flag output
Channel status emphasis control code
output
3-wire type microcomputer interface data
output
3-wire type microcomputer interface clock
input
3-wire type microcomputer interface load
input
YM3436DK (XG948E00) DIR2 (Digital Format Interface Receiver)
CPU: IC165
PIN
NO.
I/O FUNCTIONNAME
PIN
NO.
I/O FUNCTIONNAME
1
2
3
4
5
6
7
8
Vss
MCLK
DM0
DM1
RSTN
WCIN
DIN
V
DD
I
I
I
I
I
I
Ground
Master clock input
DIN/BCLK/WCLK format select
DM1,DM0=0,0 DSP,LDSP (64 bit,LSB first)
DM1,DM0=0,1stereo,DSP (64 bit,MSB first)
DM1,DM0=1,0 DSP2 (128 bit,MSB first)
DM1,DM0=1,1 BB (64 bit,MSB first)
System reset
Word clock input
Digital audio serial data input
Power supply (+5 V)
9
10
11
12
13
14
15
16
MUTE
VFL
CCK/CCB
CIN/UDB
CLD/AUXTN
CNTR/BLKIN
CSM
DOUT
I
I
I
I
I
I
I
O
Mute
Validity flag
C,U bit clock input/C bit data input
C,U bit data input/U bit data input
End of C,U bit input/16,20 bit/24 bit select
32 bit counter reset/Top of block
Channel status input mode select
CSM=0 Asynchronous mode,
CSM=1 Synchronous mode
Digital interface formatted data output
YM3437C-F (XM530A00) DIT2 (Digital Format Interface Transmitter)
CPU: IC148, 149
YM3436DK (XG948E00) DIR2 (Digital Format Interface Receiver)····················································· 19
YM3437C-F (XM530A00) DIT2 (Digital Format Interface Transmitter) ················································ 19
SH7709A (XY065A00) CPU················································································································· 20
YSS910-S (XV988A00) DSP6 (Digital Signal Processor) ···································································· 21
YSS916-H (XW867A00) CNV3 DSP (Convolver)················································································· 22
MBCG46183-129 (XV833A00) Gate Array·························································································· 23
YSD917-ME2 (XW526A00) DIR5 (Digital Format Interface Receiver)················································· 23