YMF744B Preliminary DS-1S OVERVIEW YMF744B (DS-1S) is a high performance audio controller for the PCI Bus. DS-1S consists of two separated functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine. The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without utilizing the CPU or causing system latency.
YMF744B LOGOS GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and indicates GM system level 1 Compliant. XG logo is a trademark of YAMAHA Corporation. SONDIUS-XG logo is a trademark that Stanford University in the United States and YAMAHA Corporation hold jointly. Sensaura logo is a trademark of Central Research Laboratories Limited. 1.
YMF744B PIN CONFIGURATION 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 AD27 AD28 PVSS5 AD29 AD30 AD31 REQ# GNT# PCICLK RST# PVSS6 PVDD3 RESERVE0 INTA# CVDD2 RESERVE1 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 TXD RXD YMF744B-V (0.
YMF744B 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 AD25 PVDD2 AD26 AD27 AD28 PVSS5 AD29 AD30 AD31 REQ# GNT# PCICLK RST# PVSS6 PVDD3 RESERVE0 INTA# CVDD2 RESERVE1 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 TXD RXD TEST# VDD2 VSS3 YMF744B-R (0.
YMF744B PIN DESCRIPTION 1.
YMF744B 3. External Audio Interface (5-pin) Name I/O Type Size Function SPDIFOUT O T 2mA Digital Audio Interface output SPDIFIN I Tup - Digital Audio Interface input ZVBCLK I Tup - Zoomed Video Port Bit Clock ZVLRCK I Tup - Zoomed Video Port L/R Clock ZVSDI I Tup - Zoomed Video Port Serial Data 4.
YMF744B 6. Power Supply (22-pin) Name I/O Type Size Function PVDD[3:0] - - - 3.3V Power supply for PCI Bus Interface PVSS[6:0] - - - Ground for PCI Bus Interface CVDD[2:0] - - - 3.3V Power supply for Core logic VDD[2:0] - - - 3.3V Power supply VSS[3:0] - - - Ground LVDD - - - 3.3V Power supply for PLL Filter I/O Type Size RESERVE0 O Pod - RESERVE[3:2] I Tup - RESERVE[16:8,1] - - - 7.
YMF744B EEPROM I/F SPDIF Input GPIO ZV Port PCI Side Band PC/PCI S-IRQ Selector BLOCK DIAGRAM SPDIF Output Legacy Audio FM Synthesizer SB Pro D-DMA Engine PCI Interface SRC Sampling Converter MPU401 Joystick Audio Function Config Register AC-Link Interface Revision2.1 PCI Bus Master DMA Controller PCI Native Audio XG Synthesizer DirectSound Acc.
YMF744B FUNCTION OVERVIEW 1. PCI INTERFACE DS-1S supports the PCI bus interface and complies to PCI revision 2.2. 1-1. PCI Bus Command DS-1S supports the following PCI Bus commands. 1-1-1.
YMF744B 1-2. PCI Configuration Register In addition to the Configuration Register defined by PCI Revision 2.2, DS-1S provides proprietary PCI Configuration Registers in order to control legacy audio function, such as FM Synthesizer, Sound Blaster Pro, MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation. The following shows the overview of the PCI Configuration Register. Offset b[31..24] b[23..16] b[15..8] b[7..
YMF744B 00-01h: Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Vendor ID b[15:0] ........Vendor ID This register contains the YAMAHA Vendor ID registered in Revision 2.2. This register is hardwired to 1073h. 02-03h: Device ID Read Only Default: 0010h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Device ID b[15:0] ........
YMF744B b6................PER: Parity Error Response This bit enables DS-1S responses to Parity Error. “0”: DS-1S ignores all parity errors. “1”: DS-1S performs error operation when DS-1S detects a parity error. b8................SER: SERR# Enable This bit enables DS-1S to drive SERR#. “0”: Do not drive SERR#. (default) “1”: Drives SERR# when DS-1S detects an Address Parity Error on normal target cycle or a Data Parity Error on special cycle.
YMF744B 08h: Revision ID Read Only Default: 02h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Revision ID b[7:0] ..........Revision ID This register contains the revision number of DS-1S. This register is hardwired to 02h. 09h: Programming Interface Read Only Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Programming Interface b[7:0] ..........Programming Interface This register indicates the programming interface of DS-1S.
YMF744B 0Dh: Latency Timer Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Latency Timer b[7:0] ..........Latency Timer When DS-1S becomes a Bus Master device, this register indicates the initial value of the Master Latency Timer. 0Eh: Header Type Read Only Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Header Type b[7:0] ..........Header Type This register indicates the device type of DS-1S. This is hardwired to 00h.
YMF744B 14-17h: Legacy Audio I/O Base Address (Dummy for SB, FM, MPU, D-DMA) Read / Write Default: 00000001h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 IOBASE0 b5 b4 b3 b2 b1 b0 - - - - - I/O b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 - - - - - - - - - - - - - - - - b0................IO (Read Only) This bit indicates that the base address is assigned to I/O. This bit is hardwired to “1”. b[15:6] ........
YMF744B 2C-2Dh: Subsystem Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem Vendor ID b[15:0] ........Subsystem Vendor ID This register contains the Subsystem Vendor ID. In general, this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor. This register is read only. write the IHV’s Vendor ID, use 44-45h (Subsystem Vendor ID Write Register).
YMF744B 34h: Capability Register Pointer Read Only Default: 50h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Capability Register Pointer b[7:0] ..........Capability Register Pointer This register indicates the offset address of the Capabilities register in the PCI Configuration register when 58-59h: ACPI Mode register, ACPI bit is “0”. registers as the capabilities.
YMF744B 3Fh: Maximum Latency Read Only Default: 19h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Maximum Latency b[7:0] ..........Maximum Latency This register indicates how often DS-1S generates the Bus Master Request. This register is hardwired to 19h. 40-41h: Legacy Audio Control Read / Write Default: 907Fh Access Bus Width: 8, 16, 32-bit b15 b14 LAD SIEN b13 b12 b11 b10 MPUIRQ b9 b8 b7 SBIRQ b6 SDMA b5 b4 I/O MIEN b3 b2 b1 MEN GPEN FMEN SBEN b0................
YMF744B b4................MIEN: MPU401 IRQ Enable This bit enables the interrupt service of MPU401, when LAD is set to “0” and MEN is set to “1”. MPU401 generates an interrupt signal when it receives any kind of MIDI data from the RXD pin. “0”: The MPU401 block can not use the interrupt service. “1”: The MPU401 block can use interrupt signals determined by the MPUIRQ bits. (default) b5................
YMF744B b14..............SIEN: Serialized IRQ enable DS-1S supports 3 types of interrupt protocols: PCI interrupt (INTA#), Legacy interrupt (IRQs) and Serialized IRQ. The interrupt protocol is selected with IMOD and SIEN as follows. The interrupt channels for IRQs and Serialized IRQ are determined by SBIRQ and MPUIRQ,. Only one protocol can be used at once. SIEN IMOD Interrupt protocol 0 0 Legacy interrupt (IRQs) 0 1 PCI interrupt (INTA#) 1 * Serialized IRQ (default) b15..............
YMF744B b[14:13] ......SBVER: SB Version Select These bits set the version of the SB Pro DSP. The value set in these bits is returned by sending the E1h DSP command. “0”: ver 3.01 “1”: ver 2.01 “2”: ver 1.05 “3”: reserved (default) b15..............IMOD: Legacy IRQ mode The legacy interrupt protocol is selected with IMOD and SIEN. Refer to the explanation of SIEN bit.
YMF744B 48-49h: DS-1S Control Read / Write Default: 0001h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 - - - - - - - - - - - - b3 b2 ACLS WRST B1 b0 - CRST b0................CRST: AC’97 Software Reset Signal Control This bit controls the CRST# signal. “0”: Inactive (CRST#=High) “1”: Active (CRST#=Low) (default) b2................
YMF744B 4A-4Bh: DS-1S Power Control 1 Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 - JSR - - - DPLL - DMC b0................DMC: Disable Master Clock Oscillation Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz). “0”: Normal (default) “1”: Disable b2................
YMF744B b12..............PR4: AC’97 Power Down Control 4 This bit controls the power state of the AC-link in the Primary AC’97. “0”: Normal (default) “1”: Power down b13..............PR5: AC’97 Power Down Control 5 Setting this bit to “1” disables the internal clock of the Primary AC’97. DS-1S, the master clock is supplied from DS-1S.
YMF744B 4E-4Fh: DS-1S Power Control 2 Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 - - - PSHWV PSIO b10 b9 PSACL PSDIR b8 b7 PSDIT PSZV b6 b5 b4 b3 b2 PSSRC PSPCA PSJOY PSMPU PSSB b1 b0 PSFM CMCD b0................CMCD: CODEC Master Clock Disable Setting this bit to “1” disables the oscillation of the CMCLK. To stop a clock, when the CMCLK is supplied to the AC’97, it is required that b13:PR5 bit of 4A-4Bh register is set to “1”.
YMF744B b7................PSZV: Power Save Zoomed Video port Setting this bit to “1” stops a clock supplied to the Zoomed Video port block. “0”: Normal (default) “1”: Disable b8................PSDIT: Power Save Digital Audio Interface Transmitter Setting this bit to “1” stops a clock supplied to the DIT block. “0”: Normal (default) “1”: Disable b9................PSDIR: Power Save Digital Audio Interface Receiver Setting this bit to “1” stops a clock supplied to the DIR block.
YMF744B CMCD PSFM PSSB PSMPU PSJOY PSPCA Master Clock (24.576MHz) PLL PSSRC PSZV DPLL DMC PSDIT PSDIR PSHWV PSACL AC97 Master Clock FM Synthesizer SB Pro MPU401 Joystick PCI Audio SRC ZVport SPDIF out SPDIF in H/W Vol. AC-link PCI I/F PC/PCI S-IRQ EEPROM I/F PCI Clock (33MHz) PSIO External Input I/O Pad Power Management Block 50h: Capability ID Read Only Default: 01h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Capability ID b[7:0] ..........
YMF744B 51h: Next Item Pointer Read Only Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Next Item Pointer b[7:0] ..........Next Item Pointer DS-1S does not provide other new capability besides Power Management. This register is hardwired to 00h. 52-53h: Power Management Capabilities Read Only Default: 0401h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 - - - - - D2S - - - - - - - b2 b1 b0 Version b[2:0] ..........
YMF744B 58-59h: ACPI Mode Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - - - - - - - - - ACPI b0................ACPI: ACPI Mode Select This bit select either PCI Bus Power Management or ACPI Mode for power management of DS-1S. “0”: PCI Bus Power Management is used. (34h) are enabled. CAP bit (06-07h: Status Register) and Capabilities Pointer (default) “1”: ACPI Mode is used.
YMF744B b4................SPR4: Secondary AC’97 Power Down Control 4 This bit controls the power state of the AC-link in the Secondary AC’97. “0”: Normal (default) “1”: Power down b5................SPR5: Secondary AC’97 Power Down Control 5 Setting this bit to “1” disables the internal clock of the Secondary AC’97. DS-1S, the master clock is supplied from DS-1S.
YMF744B 64-65h: MPU401 Base Address Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 MPU401 Base Address b0 - b[15:1] ........MPU401 Base Address This register sets the base address of the MPU401. If b5:I/O bit of 40h register is set to “1”, b[9:1] bits are decoded by ignoring b[15:10] bits.
YMF744B 2. ISA Compatible Device DS-1S contains the following functions to maintain the compatibility with the past ISA Sound Devices. These devices are considered Legacy devices and the functions are referred to as Legacy Audio. Legacy Audio is independent from PCI Audio and can be used simultaneously. The configuration is set in the Legacy Audio Control Register in the PCI Configuration Register space. Basically, these registers are configured by the BIOS.
YMF744B DS-1S supports PC/PCI and D-DMA protocols to emulate the DMA of SB Pro on the PCI. In addition, DS- 1S supports the old type of interrupts used by ISA and the Serialized IRQ protocol. Yamaha recommends the combination of PC/PCI and Serialized IRQ. The system block diagram when using Intel chip set is shown below.
YMF744B 2-1. FM Synthesizer Block FM Synthesizer Block is register compatible with YMF289B. However, Power Management register has been deleted because it is now controlled by the PCI Configuration Register. The following shows the FMBase I/O map of FM Synthesizer. FMBase (R) Status Register port FMBase (W) Address port for Register Array 0 FMBase+1 (R/W) Data port FMBase+2 (W) Address port for Register Array 1 FMBase+3 (R/W) Data port The default FMBase value is 0x0388.
YMF744B 2-1-2.
YMF744B 2-2. Sound Blaster Pro Block This block emulates the DSP commands of Sound Blaster and Sound Blaster Pro. functions are supported (record functions are not supported). Only playback However, to maintain compatibility for games, it is designed so that every DSP command receives a correct response. The DMA transfer of this block uses PC/PCI or D-DMA protocol. The following shows the SBBase I/O map of SB Pro.
YMF744B 2-2-1. DSP Command The following shows the list of DSP Commands that are supported by the SB Pro engine. Both SB and SB Pro commands are supported.
YMF744B 2-2-2. Sound Blaster Pro Mixer The following shows the register map of the Mixer section of Sound Blaster Pro. Address b7 b6 b5 b4 00h Voice Volume L "1" 0Ah - - - "1" 0Ch - - Ifilter* "1" 0Eh - - Ofilter* "1" 22h Master Volume L 26h 28h 2Eh b1 b0 Voice Volume R Remark - "1" MIC Volume* Input Source* "1" - "1" - St.
YMF744B (1) Volume for MIDI MIDI Vol. (26h) 0 0 Master Vol.
YMF744B 2-2-3. SB Suspend / Resume The SB block can read the internal state as to support Suspend and Resume functions. is made up of 268 flip flops. The internal state To read the state, these states are shifted in order and read 8 bits at a time from the SCAN DATA register. These registers are mapped to the SB Mixer space (see SB Mixer Register map). The registers have the following functions.
YMF744B F1h: Scan In/ Out Data Read / Write Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 SCAN DATA b[7:0] ..........SCAN DATA This is the data port for reading and writing the internal state. F2h: Current FM Synthesizer Index Read Only Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 Current FM Synthesizer Index b[7:0] ..........Current FM Synthesizer Index This register indicates current index of the FM Synthesizer.
YMF744B b7................FFEMP: FM Synthesizer Empty This bit indicates whether or not FIFO followed by the FM Synthesizer is empty.
YMF744B 2-2-4. SB IRQ Status F8h: Interrupt Flag Register Read Only Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - SBI b0................SBI: SB Interrupt Flag This bit indicates that the SB DSP occurs the interrupt. read port to clearing the interrupt and this bit. This bit is read only. Thus, read the SB DSP Then, the value of the read port is invalid. 2-3. MPU401 This block is for transmitting and receiving MIDI data. It is compatible with UART mode of “MPU401”.
YMF744B 3. DMA Emulation Protocol The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller (8237: ISA DMAC) on the system to transfer the sound data from/to the host. For DS-1S, however, ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of the Legacy Audio Block. Because signals to connect to the ISA DMAC are generally not available on the PCI bus, there are two ways proposed from the industry to emulate the ISA DMAC on the PCI bus.
YMF744B 3-2. D-DMA DS-1S provides the following registers to support D-DMA. D-DMA Slave Configuration Register (4C- 4Dh) of the PCI Configuration register is used to set the Base address of the Slave Address.
YMF744B 4. Interrupt Routing DS-1S supports three types of interrupts, interrupt signal on the PCI bus (INTA#), interrupt signal on the ISA bus (IRQ[5,7,9,10,11]), and Serialized IRQ. The IRQs on DS-1S are routed as shown below.
YMF744B 5. Hardware Volume Control The hardware volume control determines the AC’97 master volume without using any software control using the external circuit listed below. Two pins, VOLUP# for increasing the volume and VOLDW# for decreasing the volume, are used. Push SW 1k VOLUP# Push SW 1k VOLDW# 1000p 1000p DS-1S provides a shadow register for the AC’97 master volume. When the software accesses the AC’97 master volume, it is always reflected in the shadow register.
YMF744B 6. Digital Audio Interface DS-1S supports each system of the SPDIF input/output port compliant with the IEC958 specification. 6-1. SPDIF IN DS-1S provides the SPDIF input capability by switch-over operation of the zoomed video port. SPDIF input sampling frequency is 32.0kHz, 44.1kHz or 48.0kHz. In DS-1S, sampling rate of the SPDIF signal incoming from the SPDIFIN pin is converted to 48.0kHz in the frequency rate conversion stage in order to process all the signals at 48.0kHz frequency.
YMF744B 7. Zoomed Video Port Zoomed Video Port is defined in the PC Card Standard (PCMCIA) applicable to the notebook PC or other systems. This port is used to directly output video and/or audio signals onto the PCMCIA bus for D/A conversion process, and connect them directly to the video and/or audio signal processing chips on the PC system. Its major applications include MPEG decoder card and video capture card, etc.
YMF744B 8. Multiple AC’97 & Multi-Channel DS-1S allows connection with up to two AC’97s, and plays back up to 4-channel PCM data. Therefore, the following applications can be realized. 8-1. AC’97 Digital Docking AC’97 digital docking can be realized by mounting the secondary AC’97 on the docking station side. Typical example of digital docking connection between DS-1S and AC’97s is represented in the circuit diagram below.
YMF744B ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Item Symbol Min. Max. Unit VDD3 -0.3 4.6 V Input Voltage VIN -0.3 7.0 V Operating Ambient Temperature TOP 0 70 °C Storage Temperature TSTG -50 125 °C Power Supply Voltage (PVDD, VDD, CVDD, LVDD) Note : PVSS=VSS=0[V] 2. Recommended Operating Conditions Item Power Supply Voltage (PVDD, VDD, CVDD, LVDD) Operating Ambient Temperature Symbol Min. Typ. Max. Unit VDD3 3.00 3.30 3.
YMF744B 3. DC Characteristics Item Symbol Condition Min. Typ. Max. Unit -0.5 - 5.75 V High Level Input Voltage 1 VIN High Level Input Voltage 1 VIH1 *1 0.5VDD3 - 5.75 V Low Level Input Voltage 1 VIL1 *1 -0.5 - 0.3VDD3 V High Level Input Voltage 2 VIH2 *2 0.7VDD3 - 5.75 V Low Level Input Voltage 2 VIL2 *2 -0.5 - 0.3VDD3 V High Level Input Voltage 3 VIH3 *3 0.65VDD3 - 5.75 V Low Level Input Voltage 3 VIL3 *3 -0.5 - 0.
YMF744B 4. AC Characteristics 4-1. Master Clock (Fig.1) Item Symbol Min. Typ. Max. Unit XI24 Cycle Time tXICYC - 40.69 - ns XI24 High Time tXIHIGH 13 - 24 ns XI24 Low Time tXILOW 13 - 24 ns Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V 2.3 V 1.65 V XI24 1.0 V t XIHIGH t XILOW t XICYC Fig.1: XI24 Master Clock timing 4-2. Reset (Fig.2) Item Reset Active Time after Power Stable Power Stable to Reset Rising Edge Reset Slew Rate Symbol Min.
YMF744B 4-3. PCI Interface (Fig.3, 4) Item Symbol Condition Min. Typ. Max.
YMF744B 4-4. AC’97 Master Clock (Fig.5) Item Symbol Min. Typ. Max. Unit CMCLK Cycle Time tCMCYC - 40.69 - ns CMCLK High Time tCMHIGH 8 - - ns CMCLK Low Time tCMLOW 8 - ns CMCLK Rising Time tCMR - 4.6 - ns CMCLK Falling Time tCMF - 2.1 - ns Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF t CMR t CMF 0.8 VDD3 0.5 VDD3 CMCLK 0.2 VDD3 t CMHIGH t CMLOW t CMCYC Fig.
YMF744B 4-5. AC-link (Fig.6) Item Symbol Condition Min. Typ. Max. Unit CBCLK Cycle Time tCBICYC - 81.4 - ns CBCLK High Time tCBIHIGH 35 40.7 45 ns CBCLK Low Time tCBILOW 35 40.7 45 ns CSYNC Cycle Time tCSYCYC - 20.8 - ns CSYNC High Time tCSYHIGH - 1.3 - µs CSYNC Low Time tCSYLOW - 19.
YMF744B 4-6. Zoomed Video Port Item (Fig.7) Symbol Min. Typ. Max. Unit ZVLRCK Delay Time tSLRD 2 - - ns ZVLRCK Setup Time tSLRS 32 - - ns ZVBCLK Low Time tSCLKL 22 - - ns ZVBCLK High Time tSCLKH 22 - - ns ZVSDI Setup Time tSDS 32 - - ns ZVSDI Hold Time tSDH 2 - - ns Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF ZVLRCK tSLRD tSLRS ZVSCLK tSDS tSDH tSCLKH t SCLKL ZVSDI Fig.
YMF744B EXTERNAL DIMENSIONS YMF744B-V 22.00±0.40 20.00±0.30 0.15Typ. or 0.17Typ. (LEAD THICKNESS) 65 64 128 39 14.00±0.30 103 1 38 0.20±0.10 1.40±0.20 1.70MAX. P-0.50Typ. 0 Min. (STAND OFF) 16.00±0.40 102 (1.00) 0-15˚ 0.50±0.30 Unit : mm The shape of the molded corner may slightly different from the shape in this diagram. The figure in the parenthesis ( ) should be used as a reference. Plastic body dimensions do not include burr of resin.
YMF744B YMF744B-R 16.00±0.40 14.00±0.30 65 64 128 33 14.00±0.30 97 1 32 P-0.40Typ. 1.40±0.20 1.70MAX. 0.16±0.10 0 Min. (STAND OFF) 16.00±0.40 96 (1.0) 0-10˚ 0.50±0.20 LEAD THICKNESS : 0.125Typ. or 0.15Typ. Unit : mm The shape of the molded corner may slightly different from the shape in this diagram. The figure in the parenthesis ( ) should be used as a reference. Plastic body dimensions do not include burr of resin.
YMF744B IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2.