User's Manual

YMF724F
September 21, 1998
-23-
b12..............PR4: AC-2 Power down Control 4
This bit controls the power state of the AC-link in AC-2.
“0”: Normal (default)
“1”: Power down
b13..............PR5: AC-2 Power down Control 5
Setting this bit to “1” disables the internal clock of AC-2. In case AC-2 is used with DS-1, the master
clock is supplied from DS-1. Therefore, when the clock of AC-2 is stopped completely, set both PR5
and PSN bits to “1”.
“0”: Normal (default)
“1”: Disable
b[15:14] ......AC-2 Power down Control 6 and 7
The function of this bit is not supported by YAMAHA AC-2 chip. But the software can access this
register without causing an error.
Master
(24.576MHz)
PLL0
33.87MHz
PLL1
49.152MHz
OPL3
SB Pro
AC3F2 I/F
AC-2 I/F
H/W Vol.
PCI Audio
SRC
SPDIF
Legacy func. 0
PCI func. 0
DMC DPLL0
DPLL1
PSL0
PSN
PCICLK
(33MHz)
PCI I/F
PC/PCI
D-DMA
S-IRQ
PCI func. 1
MPU401
Joystick
PSL1
Legacy func. 1
- Set DPLL0, DPLL1, PSL0, PSL1 and PSN bits to “1”, when DMC bit is set to “1”.
- Set PSL0 and PSL1 bits to “1”, when DPLL0 bit is set to “1”.
- Set PSN bit to “1”, when DPLL1 bit is set to “1”.