User's Manual

YMF724F
September 21, 1998
-46-
4-4. AC-2 / AC3F2 Master Clock (Fig.5)
Item Symbol Min. Typ. Max. Unit
CMCLK Cycle Time t
CMCYC
- 40.69 - ns
CMCLK High Time t
CMHIGH
8--ns
CMCLK Low Time t
CMLOW
8-ns
CMCLK Rising Time t
CMR
-4.6-ns
CMCLK Falling Time t
CMF
-2.1-ns
Note : Top = 0-70°C, PVDD=5.0
±
0.25 V, VDD5=5.0
±
0.25 V, VDD3=3.3
±
0.3 V, LVDD=3.3
±
0.3 V, C
L
=50 pF
t
CMCLK
CMCYC
t
CMF
t
CMR
t
CMHIGH
1.0 V
2.5 V
3.5 V
t
CMLOW
Fig.5: Master Clock timing for AC-2 and AC3F2
4-5. AC-link (Fig.6)
Item Symbol Condition Min. Typ. Max. Unit
CBCLK Cycle Time t
CBICYC
- 81.4 - ns
CBCLK High Time t
CBIHIGH
35 40.7 45 ns
CBCLK Low Time t
CBILOW
35 40.7 45 ns
CSYNC Cycle Time t
CSYCYC
- 20.8 - ns
CSYNC High Time t
CSYHIGH
-1.3-ns
CSYNC Low Time t
CSYLOW
- 19.5 - ns
CBCLK to Signal Valid Delay t
CVAL
*12 - - 20 ns
Output Hold Time for CBCLK t
COH
*12 0 - - ns
Input Setup Time to CBCLK t
CISU
*13 15 - - ns
Input Hold Time for CBCLK t
CIH
*13 5 - - ns
Note) Top = 0-70°C, PVDD=5.0
±
0.25 V, VDD5=5.0
±
0.25 V, VDD3=3.3
±
0.3 V, LVDD=3.3
±
0.3 V, C
L
=50 pF
*12: This characteristic is applicable to CSYNC and CSDO signal.
*13: This characteristic is applicable to CSDI signal.