Yuga CLM920 TD5 LTE Module Hardware Manual
Table Of Contents
- 1 Introduction
- 2 Product Overview
- 2.1 General Description
- 2.2 Key Features
- 2.3 Module Function
- 3 Application Interface
- 3.1 General Description
- 3.2 Module Interface
- 3.2.1 52-pin Goldfinger
- 3.2.2 Interface definition
- 3.3 Power Interface
- 3.3.1 Power Design
- 3.3.2 Reference Design of Power Supply
- 3.3.3 VDD_EXT 1V8 output
- 3.4 Reset mode
- 3.4.1 Power-on sequence
- 3.4.2 Power off
- 3.4.3 Reset control
- 3.5 USB interface
- 3.6 UART interface
- 3.7 USIM interface
- 3.7.1 USIM card reference circuit
- 3.7.2 UIM_DET Hot-Plug Reference Design
- 3.8 General purpose GPIO interface
- 3.9 Network Indication Interface
- 3.10 Analog voice interface
- 3.10.1 Analog Voice Reference Design
- 3.10.2 Analog Voice Reference Design
- 3.11 PCM audio interface
- 3.12 Antenna Interface
- 3.12.1 RF Connector Location
- 3.12.2 RF Connector
- 4 Overall Technical Indicators
- 4.1 Overview of this chapter
- 4.2 Operating frequency
- 4.3 Conducted RF Measurements radio frequency
- 4.3.1 Test environment
- 4.3.2 Test standards
- 4.4 Conducted receive sensitivity and transmit pow
- 4.5 Antenna requirements
- 4.6 Power consumption characteristics
- 5 Interface electrical characteristics
- 5.1 Operating Storage Temperature
- 5.2 Module IO electrical characteristics
- 5.3 Power supply characteristics
- 5.4 Electrostatic characteristics
- 6 Structural and mechanical properties
- 6.1 Appearance
- 6.2 Mini PCI Express connector
- 6.3 Module fixing method
CLM920_TD5 LTE Module Hardware Manual
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AT+CSDVC=4, then connect the module to the external audio power amplifier signal.
③ The audio signal is a sensitive signal, the alignment should be careful to protect
against interference, keep away from the RF interference area, connection lines as short
as possible and protect sensitive signals when layout.
④ In order to prevent noise of TDD, design of audio circuit should reserved filter
capacitance of 10 pF and 33 pF, which to remove radio frequency interference signal.
⑤ Users can set to handset output by AT+CSDVC=4, headset output by
AT+CSDVC=2. Adjust the handset output volume gain by AT+COUTGAIN and set the
Mic gain by AT+CMICGAIN. More details refer to the AT manual.
3.11 PCM audio interface
CLM920_TD5 Mini PCIE module provides one PCM audio interface, which supports 8-bit
A-law and μ -law, 16-bit linear data formats, PCM_SYNC is 8kHZ, PCM_CLK is
2048kHZ。
Table 3- 15 PCM Pin Definition
Pin
Signal Name
I/O
Descripition
45
PCM_CLK
D0
PCM clock signal
47
PCM_DOUT
D0
PCM data output
49
PCM_DIN
DI
PCM data input
51
PCM_SYNC
DO
PCM frame sync
Table 3- 16 PCM Parameter
Feature
Descripition
Data Format
linear
Data bit
16bits
PCM role
Master/Slave
PCM Clock
2048kHz
PCM Frame Sync
short
Transfer
MSB