User's Manual

148603 Project Document

148603 Specification and Integration Guide

Confidential Material – Disclosure Strictly Prohibited. "Ni ckel Leucochroic Puffin"

2. Architecture

2.1. WLAN

2.1.1. Host Communications

The WLAN core requires a total of eight (8) dedicated signals in order to communicate

to the host processor. The WLAN core is enabled via the WL_EN signal (1) and

communicates to the host processor via SDIO (6) with an additional interrupt signal

WL_IRQ(1).

2.1.1.1. Hardware Interface

The interface between the host and the 148603 Module is a standard SDIO interface

(see SDIO spec version 2.0), supporting maximum clock rate of 52MHz.

The WL1281/3 SDIO also supports the following features:

• Both 1 and 4 bit data bus

• Abort command

• Multi-Block data transfer

• The SDIO interface is used for WLAN IP only.

• The SDIO interface supports High Speed protocol.

2.2. Bluetooth

2.2.1. Host Communications

The Bluetooth subsystem requires nine (9) connections to the host in order for full

operation, including PCM (4), High-Speed UART (4) and BT_GPS_FM_EN (1) , which

shall be connected to the host to enable the Bluetooth IP. It should also be noted that

an additional line from the WL1283 can be used for debug purposes, namely

BT_UART_DBG.

2.2.1.1. Hardware Interface

2.2.1.1.1. HCI UART Transport layers

The HCI UART Supports 4-wire UART interface to host. Supports most baud rates for

all fast clock frequencies, up to a maximum of 4Mbps. Default baud rate after power up

is 115.kkbps with a deviation of +1.5%, -2.5%, until baud is changed via a vendor

specific command.