ZedBoard (Zynq™ Evaluation and Development) Hardware User’s Guide Version 2.
Table of Contents 1 INTRODUCTION .................................................................................................................................. 2 1.1 2 ZYNQ BANK PIN ASSIGNMENTS ...................................................................................................... 4 FUNCTIONAL DESCRIPTION ............................................................................................................ 5 2.1 ALL PROGRAMMABLE SOC ..............................................
1 Introduction TM The ZedBoard is an evaluation and development board based on the Xilinx Zynq -7000 All Programmable SoC (AP SoC). Combining a dual Corex-A9 Processing System (PS) with 85,000 Series-7 Programmable Logic (PL) cells, the Zynq-7000 AP SoC can be targeted for broad use in many applications. The ZedBoard’s robust mix of on-board peripherals and expansion capabilities make it an ideal platform for both novice and experienced designers.
Figure 1 – ZedBoard Block Diagram 3 02-Oct-2013
1.1 Zynq Bank Pin Assignments The following figure shows the Zynq bank pin assignments on the ZedBoard followed by a table that shows the detailed I/O connections.
2 Functional Description 2.1 All Programmable SoC The ZedBoard features a Xilinx Zynq XC7Z020-1CLG484 All Programmable SoC (AP SoC). Initial ZedBoards were marked ‘Rev C’ and shipped with Engineering Sample "CES" grade silicon. Later ‘Rev D’ shipments switched to production "C" grade silicon once those became available. The Zynq-7000 AP SoC part markings indicate the silicon grade. 2.2 Memory Zynq contains a hardened PS memory interface unit.
The PCB design guidelines outlined in Zynq datasheet must be followed for trace matching, etc.
Pin Group Length (mm) Table 2 - DDR3 Worksheet Calculations Length Package Total Propagation Total (mils) Length Length Delay Delay (mils) (mils) (ps/inch) (ns) CLK0 55.77 2195.9 470 2665.9 160 0.427 CLK1 55.77 2195.9 470 2665.9 160 0.427 CLK2 41.43 1631.1 470 2101.1 160 0.336 CLK3 41.43 1631.1 470 2101.1 160 0.336 DQS0 51.00 2008.0 504 2512.0 160 0.402 0.025 DQS1 50.77 1998.8 495 2493.8 160 0.399 0.028 DQS2 41.59 1637.6 520 2157.6 160 0.345 -0.
The relevant device attributes are: • 256Mbit • x1, x2, and x4 support • Speeds up to 104 MHz, supporting Zynq configuration rates @ 100 MHz o In Quad-SPI mode, this translates to 400Mbs • Powered from 3.3V The SPI Flash connects to the Zynq-7000 AP SoC supporting up to Quad-I/O SPI interface. This requires connection to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in the Zynq datasheet.
Two packages can be used on the ZedBoard; SO-16 and WSON. For the WSON package, there is a heat sink slug under the package that is not connected to any signal on the PCB.
2.2.3 SD Card Interface The Zynq PS SD/SDIO peripheral controls communication with the ZedBoard SD Card (A 4GB Class 4 card is included in the ZedBoard kit.) The SD card can be used for non-volatile external memory storage as well as booting the Zynq-7000 AP SoC. PS peripheral sd0 is connected through Bank 1/501 MIO[40-47], including, Card Detect and Write Protect. The SD Card is a 3.3V interface but is connected through MIO Bank 1/501 (1.8V).
2.3 USB 2.3.1 USB OTG Warning: After the design of the ZedBoard was complete, a timing incompatibility between the TUSB1210 PHY and Zynq was discovered. The TUSB1210 is not recommended for new designs with Xilinx Zynq. Please refer to the ZedBoard Errata for more details. ZedBoard implements one of the two available PS USB OTG interfaces. An external PHY with an 8-bit ULPI interface is required. A TI TUSB1210 Standalone USB Transceiver Chip is used as the PHY.
The UART 1 Zynq PS peripheral is accessed through MIO[48:49] in MIO Bank 1/501 (1.8V). Since the CY7C64225 device requires either 3.3V or 5V signaling, a TI TXS0102 level shifter is used to level shift between 3.3V and 1.8V. This USB port will not power the board. Therefore, Vbus needs to be connected to 3.3V though a 1KΩ series resistor. The Wake pin, pin 22, connects to GND. A 24Ω series resistor was placed on each of the data lines, D+ and D-.
2.3.4 USB circuit protection All USB data lines, D+/-, are protected with a TE SESD0402Q2UG-0020-090. USB Con n D+ D- Level Shifter Figure 8 – ESD Protection 2.4 2.4.1 Display and Audio HDMI Output An Analog Devices ADV7511 HDMI Transmitter provides a digital video interface to the ZedBoard. This 225MHz transmitter is HDMI 1.4- and DVI 1.0-compatible supporting 1080p60 with 16-bit, YCbCr, 4:2:2 mode color. The ADV7511 supports both S/PDIF and 8-channel I2S audio.
Signal Name HDP HD-INT HD-SCL HD-SDA HD-CLK HD-VSYNC HD-HSYNC HD-DE HD_D[15:0] HD-SPDIF HD-SPDIFO Table 7 - HDMI Interface Connections Description Zynq pin Hot Plug Detect signal input N/C Interrupt signal output W16 I2C Interface. Supports CMOS AA18 logic levels from 1.8V to 3.3V Y16 Video Clock Input. Supports typical CMOS logic levels from 1.8V up to 3.
Figure 9 - HDMI Video Interface Timing The HDMI transmitter connects externally via a HDMI Type A connector, J9, TE 1903015-1. Circuit protection for the HDMI interface is provided by a Tyco Electronics SESD0802Q4UG.
2.4.2 VGA Connector The ZedBoard also allows 12-bit color video output through a through-hole VGA connector, TE 41734682-2. Each color is created from resistor-ladder from four PL pins.
2.4.3 I2S Audio Codec An Analog Devices ADAU1761 Audio Codec provides integrated digital audio processing to the Zynq-7000 AP SoC. It allows for stereo 48KHz record and playback. Sample rates from 8KHz to 96KHz are supported. Additionally, the ADAU1761 provides digital volume control. The Codec can be configured using Analog Devices SigmaStudio™ for optimizing audio for specific acoustics, numerous filters, algorithms and enhancements. Analog Devices provides Linux drivers for this device. http://www.
2.4.4 OLED An Inteltronic/Wisechip UG-2832HSWEG04 OLED Display is used on the ZedBoard. This provides a 128x32 pixel, passive-matrix, monochrome display. The display size is 30mm x 11.5mm x 1.45mm.
2.6.2 Program Push Button Switch A PROG push switch, BTN6, toggles Zynq PROG_B. This initiates reconfiguring the PLsubsection by the processor. 2.6.3 Processor Subsystem Reset Power-on reset, labeled PS_RST/BTN7, erases all debug configurations. The external system reset allows the user to reset all of the functional logic within the device without disturbing the debug environment. For example, the previous break points set by the user remain valid after system reset.
2.7.3 User LEDs The ZedBoard has eight user LEDs, LD0 – LD7. A logic high from the Zynq-7000 AP SoC I/O causes the LED to turn on. LED’s are sourced from 3.3V banks through 390Ω resistors. Table 14 - LED Connections Signal Name Subsection Zynq pin LD0 PL T22 LD1 PL T21 LD2 PL U22 LD3 PL U21 LD4 PL V22 LD5 PL W22 LD6 PL U19 LD7 PL U14 LD9 PS D5 (MIO7) 2.8 10/100/1000 Ethernet PHY The ZedBoard implements a 10/100/1000 Ethernet port for network connection using a Marvell 88E1518 PHY.
Signal Name RX_CLK RX_CTRL RXD[3:0] TX_CLK TX_CTRL TXD[3:0] MDIO MDC Table 15 – Ethernet PHY Pin Assignment and Definitions Description Zynq pin MIO Receive Clock A14 Receive Control D7 Receive Data RXD0: E11 RXD1: B7 RXD2: F12 RXD3: A13 16:27 Transmit Clock D6 Transmit Control F11 Transmit Data TXD0: E9 TXD1: A7 TXD2: E10 TXD3: A8 Management Data C12 52:53 Management Clock D10 88E1510 pin 40 37 38 39 41 42 47 2 44 45 48 1 5 4 The datasheet for the Marvell 88E1518 is not available publicly.
2.9.2 Digilent Pmod™ Compatible Headers (2x6) The ZedBoard has five Digilent Pmod™ compatible headers (2x6). These are right-angle, 0.1” female headers that include eight user I/O plus 3.3V and ground signals as show in the figure below. Four Pmod connectors interface to the PL-side of the Zynq-7000 AP SoC. These will connect to Bank 13 (3.3V). One Pmod, JE1, connects to the PS-side on MIO pins [7,9-15] in MIO Bank 0/500 (3.3V).
Pmod JA1 Pmod JC1 Differential Table 16 - Pmod Connections Pmod Zynq pin Signal Name Signal Name JA1 JA2 JA3 JA4 JA7 JA8 JA9 JA10 Y11 AA11 Y10 AA9 AB11 AB10 AB9 AA8 Signal Name JC1_N JC1_P JC2_N JC2_P JC3_N JC3_P JC4_N JC4_P JB1 Zynq pin AB6 AB7 AA4 Y4 T6 R6 U4 T4 Pmod JE1 MIO Pmod Pmod JD1 Differential Signal Name JE1 JE2 JE3 JE4 JE7 JE8 JE9 JE10 Zynq pin JB1 JB2 JB3 JB4 JB7 JB8 JB9 JB10 W12 W11 V10 W8 V12 W10 V9 V8 Signal Name JD1_N JD1_P JD2_N JD2_P JD3_N JD3_P JD4_N JD4_P Zynq pin W7 V
The ZedBoard AMS header is comparable with similar connectors on the Xilinx KC705 and ZC702 boards. Any AMS plug-in cards built for those boards should be compatible with ZedBoard as well.
Table 17 - Analog Header Pin Out Name VP/VN VAUX0P/VAUX0N Description Requirement XADC Header Zynq Pin Two pins required. Dedicated pins on the 7 series package. 1V peak-topeak input 1 XADC-VN-R : M12 This is the dedicated analog input channel for the ADC(s). maximum 2 XADC-VP-R : L11 Two pins required. Auxiliary analog input channel 0. Two dedicated channels needed for simultaneous sampling applications.
2.10 Configuration Modes Zynq-7000 AP SoC devices use a multi-stage boot process that supports both non-secure and secure boot (note that secure boot is not supported for CES silicon.) The PS is the master of the boot and configuration process. The following table shows the Zynq configuration modes. Upon reset, the device mode pins are read to determine the primary boot device to be used: NOR, NAND, Quad-SPI, SD Card or JTAG. By default, the ZedBoard uses the SD Card configuration mode.
The PS boot mode selections are shown in the table below, default setting highlighted in yellow: Table 18 – ZedBoard Configuration Modes Xilinx TRM MIO[6] MIO[5] MIO[4] MIO[3] MIO[2] Boot_Mode[4] Boot_Mode[0] Boot_Mode[2] Boot_Mode[1] Boot_Mode[3] JTAG Mode Cascaded JTAG Independent JTAG 0 1 Boot Devices 0 0 1 0 1 1 PLL Mode JTAG Quad-SPI SD Card PLL Used PLL Bypassed 0 0 0 0 1 Bank Voltages MIO Bank 500 MIO Bank 501 3.3V 1.8V Expected configuration time using a 50MB/s QSPI flash is 250ms.
ZedBoard automatically adds the FMC into the JTAG chain when an FMC card is plugged into the board via the FMC-PRSNT signal. 2.11 Power 2.11.1 Primary Power Input The board’s primary input is through a 12V barrel jack. A compatible AC/DC converter will have a 2.5mm inner diameter, 5.5mm outer diameter, center positive connection. The total power budget is based on 4A from an AC/DC wall wart supply. This rail is protected with a TE 0603SFF600F/24-2.
The table below shows the minimum required voltage rails, currents, and tolerances. Table 19 - TPS65708 Connections Voltage (V) Current (A) Tolerance 1.0 (Vccint) 1.3 5.00% 1.5 (Vccoddr) 1.5 5.00% 1.8 (Vccaux) 0.8 5.00% 1.8, 2.5, 3.3 (jumper adjustable, 2.5V default) (Vadj) 2 5.00% 3.3 (Vcco/FMC/Pmod) 3 5.00% 1.8 (analog) (Vccadc) 0.15 5.00% 1.25 reference (Vrefp) 0.005 0.2%, 50ppm/ºC 0.75 (DDR3 Vtt) 1.5 5.00% 5.0 (Filtered for XADC) 0.15 5.00% 2.11.
2.11.5 Power Good LED A green status LED, LD13, indicates when power is good on the board. Power Good is wired with the Resets and PROG to prevent operation of the board when power is not good. 2.11.6 Power Estimation The Power estimation chart is shown below.
2.11.7 Testing The power circuitry has been tested to verify compliance with the Zynq power requirements, such as: • Tolerance o 1.0V Vccint 0.95 to 1.05V o Vccaux +/- 5% o Vcco +/-5% • Ramp time o 0.20 to 50ms o In-rush current must be controlled so the power circuitry is not overloaded at start-up • Monotonicity o No negative dips in Vccint or Vccaux power-up ramps • Sequencing o Verify sequencing responds as expected based on design • Refer to Zynq Datasheet for the latest requirements 2.11.
3 Zynq-7000 AP SoC Banks The following figure and table show Zynq CLG484 I/O bank assignments on the Zynq board.
3.1 Zynq-7000 AP SoC Bank Voltages Table 21 - Zynq Bank Voltage Assignments PS-Side Bank Voltage (default) MIO Bank 0/500 3.3V MIO Bank 1/501 1.8V DDR 1.5V PL-Side Bank0 3.3V Bank 13 3.3V Bank 33 3.3V Bank 34 Vadj (2.5V) Bank 35 Vadj (2.5V) Note: Banks 34 and 35 are powered from an adjustable voltage rail. Jumper, J18, selects this voltage. Selectable voltages include 1.8V, 2.5V and 3.3V. The 3.
4 Jumper Settings Table 22 - Jumper Settings Ref Designator Description Default Setting JP1 Microphone Input Bias Open – No Electret Microphone JP2 Vbus 5V Enable Open – 5V Disconnected JP3 USB Vbus Capacitor Setting Open – Device Mode JP4 CFGBVS Select Not Populated JP5 PUDC Select Not Populated JP6 PS_MIO0 Pull-Down Short Boot_Mode[3]/MIO[2] GND – Cascaded JTAG JP7 JP8 JP9 JP10 Boot_Mode[0]/MIO[3] Boot_Mode[1]/MIO[4] Boot_Mode[2]/MIO[5] 110 – SD Card JP11 Boot_Mode[4]/MIO[6] G
Figure 20 - ZedBoard Jumper Map 35 02-Oct-2013
5 Mechanical The ZedBoard measures 6.3”x6.3”.
Revision History Rev date Rev # 8/1/12 8/2/12 1.0 1.1 8/14/12 1.2 8/15/12 8/30/12 1.3 1.4 9/4/12 1.5 9/5/12 1/17/13 1.6 1.7 1/18/13 1.8 1/29/13 1.9 10/2/13 2.0 Reason for change Initial ZedBoard User’s Guide Mapped Configuration Mode Table to match ZedBoard layout Added MIO Pins and Peripheral Tables; Updated Reset Section; Updated Block Diagram Updated Part Package numbering; Matched Xilinx Trademarks Updated Board Images to Rev. C.
