Installation Instructions

Contribution to Technology · ZLG Electronics
A6G2C Series Core Board
MiniARM Core Board
Product Data Manual
©2020 Guangzhou ZHIYUAN Electronics Co., Ltd.
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Function
Signal Name
Function description
Pin No.
JTAG
JTAG_TCK
JTAG controller clock
B32
UART
UART1_RXD
UART1 data reception (debug serial port)
B46
UART1_TXD
UART1 data transmission (debug serial port)
B45
UART2_RXD
UART2 data reception
B48
UART2_TXD
UART2 data transmission
B47
UART3_RXD
UART3 data reception
B50
UART
UART3_TXD
UART3 data transmission
B49
UART4_RXD
UART4 data reception
B52
UART4_TXD
UART4 data transmission
B51
UART5_RXD
UART5 data reception
B54
UART5_TXD
UART5 data transmission
B53
UART6_RXD
UART6 data reception
A57
UART6_TXD
UART6 data transmission
A59
UART7_RXD
UART7 data reception
A23
UART7_TXD
UART7 data transmission
A24
UART8_RXD
UART8 data reception
A25
UART8_TXD
UART8 data transmission
A26
Power supply
GND
Power ground
A19
GND
Power ground
A20
GND
Power ground
A45
GND
Power ground
A46
GND
Power ground
A52
GND
Power ground
A77
GND
Power ground
A79
5V_IN
Main power supply pin of the core board
A78
5V_IN
Main power supply pin of the core board
A80
GND
Power ground
B20
GND
Power ground
B21
GND
Power ground
B44
GND
Power ground
B59
3V_BAT
CPU internal RTC battery interface
B60
The BOOT_MODE boot configuration in the preceding table has priority over the BT_CFG1 boot
configuration.
The VREF_ADC pin in the preceding table is the external reference voltage adjustment pin of the ADC.
The internal configuration is 3.3 V, which cannot be modified. This pin has no adjustment function.
3.5 Common Interface Multiplexing of the A6G2C Series Core Board
Here, the maximum number that each interface can achieve is divided. Pay attention to its multiplexing
relationship with other interfaces during use to avoid functional conflicts.