Installation Instructions

Contribution to Technology · ZLG Electronics
A6G2C Series Core Board
MiniARM Core Board
Product Data Manual
©2020 Guangzhou ZHIYUAN Electronics Co., Ltd.
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Signal
Description
Chip corresponding pin
Direction
ADC2_IN3
A/D converter 2 input channel 3
GPIO1_IO03
Input
ADC2_IN4
A/D converter 2 input channel 4
GPIO1_IO04
Input
ADC2_IN5
A/D converter 2 input channel 5
GPIO1_IO05
Input
ADC2_IN6
A/D converter 2 input channel 6
GPIO1_IO06
Input
ADC2_IN7
A/D converter 2 input channel 7
GPIO1_IO07
Input
ADC2_IN8
A/D converter 2 input channel 8
GPIO1_IO08
Input
ADC2_IN9
A/D converter 2 input channel
GPIO1_IO09
Input
Note 1: The 10 channels of ADC1 share GPIO1_IO00 - GPIO1_IO09 with the 10 channels of ADC2.
The A6G2C series core board has re-allocated resources to GPIO1_IO00~GPIO1_IO09. The default
configuration of the system firmware is as follows. If you need multiple ADCs, you can configure them after
careful check.
Table 3.27 Default configuration of GPIO1_IO00 - GPIO1_09 pins of A6G2C series core boards
Chip corresponding pin
Default firmware
function
Pin number
Description
Direction
GPIO1_IO00
USB_OTG1_ID
B23
USB_OTG1_ID signal
Input
GPIO1_IO01
TS_YN
B57
Touch screen YPLL signal
Input
GPIO1_IO02
TS_YP
B58
Touch screen YNLR signal
Input
GPIO1_IO03
TS_XN
B55
Touch screen XPUL signal
Input
GPIO1_IO04
TS_XP
B56
Touch screen XNUR signal
Input
GPIO1_IO05
USB_OTG2_ID
B24
USB_OTG2_ID signal
Input
GPIO1_IO06
ENET_MDIO
A1
Ethernet management data
signals
Input/Output
GPIO1_IO07
ENET_MDC
A2
Ethernet management clock
signal
Output
GPIO1_IO08
ADC1_IN8
B41
ADC1 channel 8
Input
GPIO1_IO09
ADC1_IN9
B39
ADC1 channel 9
Input
Note 1: The A6G2C series core boards do not support ADC2;
Note 2: The firmware of A6G2C series core board is configured with ADC1 channel 8 and channel 9 by
default, and the other channels have been reused by other functions.
3.5.8 JTAG
The A6G2C series core board supports one JTAG debug interface, which can be used as debug function and
GPIO function. When it is used as a GPIO function, adding a 0.1μF filter capacitor to the signal pins in Table 3.28
can effectively protect against EMC. When it is used as a debugging function, a filter capacitor cannot be added;
otherwise, the kernel cannot be connected and thus debugging is disabled. Design the circuit according to your
actual application.
Table 3.28 A6G2C series core board JTAG default configuration
Pin number
Chip corresponding pin
Default firmware function
Reusable function
Remarks
B32
JTAG_TCK
TAP controller clock
GPIO
Firmware default JTAG
functionality
B34
JTAG_nRST
TAP controller reset
B36
JTAG_TMS
TAP controller mode
selection
B38
JTAG_TDI
TAP controller data input
B40
JTAG_TDO
TAP controller data output