User's Manual
Table Of Contents
- ZTEWelink Hardware Development Guide of ZM8620_V2 Module Product_V2.3.pdf
- Legal Information
- 1 About This Document
- 2 Product Overview
- 3 Mechanic Feature
- 4 Pin Description
- 5 Electric Feature
- 6 Related Test & Testing Standard
- 7 RF Specifications
- 8 Antenna
- 9 Debugging Environment and Method
- 10 Package System
- 11 Safety Information
- 12
Hardware Development Guide of Module Product
All Rights reserved, No Spreading abroad without Permission of ZTEWelink 18
错误!未找到
用源。
ZM8620_V2
NOTE:
The voltage design of external circuit interfaces should match that of the ZM8620_V2 PINs.
In the Table 4-2, the Power supply of ZM8620_V2 has been updated between 3.1V-3.6V, and the typical
value is 3.3V at present. While in ZM8620 module, the Power supply is 3.4-4.2V, and typical is 3.8V
before.
In ZM8620_V2, the signal of pin 6,11,13,16,17,23,25,28,30~33,44,46.48 is different from that of
module ZM8620.
4.2 Feature of Interface Power Level
4.2.1 Power Level of IO Interface
Table 4–3 Power Level Range of Digital Signal
Signal
Description
Min
Max
Units
VIH
High level of input voltage
0.65*VDD_PX
VDD_PX+0.3
V
VIL
Low level of input voltage
-0.3
0.35*
VDD_PX
V
VOH
High level of output
voltage
VDD_PX-0.45
VDD_PX
V
VOL
Low level of output
voltage
0
0.45
V
NOTE:
1. The high/low PWL of input voltage should comply with the range in the table.
2. The high/low PWL of external interface signal should match the interface PWL of ZM8620_V2.
3. VDD_PX indicates the typical voltage of each Pin specified in Table 4-2.