User's Manual
Table Of Contents
- ZTEWelink Hardware Development Guide of ZM8620_V2 Module Product_V2.3.pdf
- Legal Information
- 1 About This Document
- 2 Product Overview
- 3 Mechanic Feature
- 4 Pin Description
- 5 Electric Feature
- 6 Related Test & Testing Standard
- 7 RF Specifications
- 8 Antenna
- 9 Debugging Environment and Method
- 10 Package System
- 11 Safety Information
- 12
Hardware Development Guide of Module Product
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ZM8620_V2
4.8 Reset Signal PERST#
The PERST# signal (PIN No: 22) is the system reset signal of ZM8620_V2, active low. Table 4-7
illustrates its control logic. It shows that pull down the reset key (PERST#) to 100ms will reset the
module.
NOTE:
Do not directly connect this signal to the positive end of power supply.
Table 4–7 Definition and Description of PERST# Signal
PERST#
ZM8620_V2 Status
‗1‘
ZM8620
_V2
is in the
normal working status.
‗0‘ and ≥100ms
RF is in the OFF mode,
ZM8620
_V2
is reset.
Figure 4–6 Reference Circuit Design of PERST# Signal
4.9 WAKE# Signal
Figure 4-7 illustrates the reference connection circuit of WAKE# signal. The WAKE# signal (PIN No.: 1)
is an output signal, active low level or low fall edge. This signal is a reserved signal for ZM8620_V2 to
wake up the system host. ZM8620_V2 pulls up the power level to VDD_3V3 internally by the 10Kohm
resistance. It is recommended to connect the 47ohm resistance to the GPIO PIN on the main chip (If this
GPIO PIN is on the system side, it can wake up the host).
ZM8620_V2