User guide

Compaq StorageWorks RAID Array 4000 User Guide
By serving as a posted write cache and read-ahead cache, the array accelerator
dramatically improves the performance of read and write commands. The
array accelerator is particularly useful for increasing performance in database
and fault tolerant configurations.
The array accelerator increases performance by having the array controller
write data to the cache memory on the array accelerator rather than directly to
the drives. The system can access this cache memory more than 100 times
faster than accessing disk storage. The array controller writes the data in the
array accelerator to the drive array at a later time, when the controller is
otherwise idle.
The array controller also uses the array accelerator to increase performance by
anticipating requests. The array accelerator uses a multi-threaded algorithm to
predict the next likely read operation for the array. That data is pre-read into
the array accelerator and therefore is ready before you access it.
The array accelerator was designed to protect data integrity. Batteries and ECC
memory protect the cache memory. This allows users to take full advantage of
the performance without sacrificing reliability.
The array accelerator was also designed to be removable as a complete unit.
This, along with the integrated batteries, means that the array accelerator may
be removed from one RA4000 Array Controller and installed on another. If
there is any data in the array accelerator that has not been written to the hard
drive, it may be physically transferred to another array controller. This might
happen if the array controller or server failed before the cached data could be
stored on a drive.
To assure further data integrity, the array accelerator cache is made up of ECC
memory. ECC (Error Checking and Correcting) memory will detect and
correct all single-bit memory errors in multiple DRAMs. It will also detect all
two-bit memory errors in any position and most three- and four-bit memory
errors in a single DRAM. An entire DRAM can also fail without data loss.
This ensures the correction of common memory errors without interrupting
system operation.