Specifications

Chapter 2 - Microcontroller PIC16F84
C bit is affected by ADDWF, ADDLW, SUBLW, SUBWF instructions.
bit 1 DC (Digit Carry) DC Transfer
Bit affected by operations of addition, subtraction and shifting. Unlike C bit, this bit represents
transfer from the fourth resulting place. It is set by addition when occurs carry from bit3 to bit4,
or by subtraction when occurs borrow from bit4 to bit3, or by shifting in both direction.
1=transfer occured on the fourth bit according to the order of the result
0=transfer did not occur
DC bit is affected by ADDWF, ADDLW, SUBLW, SUBWF instructions.
bit 2 Z (Zero bit) Indication of a zero result
This bit is set when the result of an executed arithmetic or logic operation is zero.
1=result equals zero
0=result does not equal zero
bit 3 PD (Power-down bit)
Bit which is set whenever power supply is brought to a microcontroller as it starts running, after
each regular reset and after execution of instruction CLRWDT. Instruction SLEEP resets it when
microcontroller falls into low consumption/usage regime. Its repeated setting is possible via reset
or by turning the supply on, or off . Setting can be triggered also by a signal on RB0/INT pin,
change on RB port, completion of writing in internal DATA EEPROM, and by a watchdog, too.
1=after supply has been turned on
0= executing SLEEP instruction
bit 4 TO Time-out ; Watchdog overflow.
Bit is set after turning on the supply and execution of CLRWDT and SLEEP instructions. Bit is reset
when watchdog gets to the end signaling that something is not right.
1=overflow did not occur
0=overflow did occur
bit6:5 RP1:RP0 (Register Bank Select bits)
These two bits are upper part of the address for direct addressing. Since instructions which
address the memory directly have only seven bits, they need one more bit in order to address all
256 bytes which is how many bytes PIC16F84 has. RP1 bit is not used, but is left for some future
expansions of this microcontroller.
01=first bank
00=zero bank
bit 7 IRP (Register Bank Select bit)
Bit whose role is to be an eighth bit for indirect addressing of internal RAM.
1=bank 2 and 3
0=bank 0 and 1 (from 00h to FFh)
STATUS register contains arithmetic status ALU (C, DC, Z), RESET status (TO, PD) and bits for
selecting of memory bank (IRP, RP1, RP0). Considering that selection of memory bank is
controlled through this register, it has to be present in each bank. Memory bank will be discussed
in more detail in Memory organization chapter. STATUS register can be a destination for any
instruction, with any other register. If STATUS register is a destination for instructions which affect
Z, DC or C bits, then writing to these three bits is not possible.
OPTION register
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