Specifications

Red Hat Enterprise Linux to Oracle Solaris Porting Guide
17
Chapter 3 Operating System Considerations
Supported Processor Architectures (Linux Versus Oracle Solaris)
Many factors have resulted in increased use of Linux systems during last decade; in particular,
significant popularity was observed in desktop systems and to some extent in the server systems
market as well. One of the major reasons for this increase in deployments was the desire to decrease
system costs. Though various flavors of Linux are available on SPARC (RISC) platforms, most Linux
deployments happened on x86/x64 systems. On the other hand, most enterprise deployments
continue to happen on RISC platforms due to their inherent reliability, stability, availability, and
scalability.
Oracle Solaris 11 is designed to address both of these markets. The availability of Oracle Solaris on
x86/x64 and SPARC platforms, along with the source code compatibility guarantee across processor
architectures offered by Oracle, makes development on Oracle Solaris a compelling proposition.
Migrating from Linux to Oracle Solaris while remaining on an x86/x64 system is a simple task because
few processor-specific issues arise during this transition. On the other hand, specific measures must be
taken when transitioning to a SPARC/RISC platform.
The next few sections discuss in detail the various aspects that must be considered during migration
from an x86/x64 system to an Oracle Solaris SPARC platform.
Storage Order and Alignment
Default Alignment and Recommendations
Every data type has alignment requirements mandated by the processor architecture. A processor will
be able to efficiently process data if the processing word size matches processor's data bus size. For
example, on a 32-bit machine, the processing word size is 4 bytes.
The reason for not permitting misaligned long-word reads and writes is obvious. For example, an
aligned integer A would be written as A0, A1, A2, and A3 in the memory (4 bytes). If this integer is
stored with proper alignment, the processor can read the complete word in a single bus cycle.
Figure 3-1. A properly aligned integer value can be read in a single fetch operation.
If the same processor now attempts to access an integer at an unaligned address, it will have to read
bytes X0, X1, X2, and X3 (see Figure 3.2). This read cannot be performed in a single 32-bit bus cycle.