HP Advanced Memory Error Detection Technology

Introduction

Across the industry, memory errors have increased significantly due to the growth in overall server

memory capacity and the increase in the number of bits per DRAM chip. Uncorrectable memory

errors can cause applications and operating systems to crash, so they are costly in terms of downtime

and repairs.

Over the past 18 years, HP has introduced several memory technology innovations to ensure data

reliability and protection. In 1999, we introduced the Pre-Failure Alert notification system to monitor

and predict potential problems with critical components such as system memory modules (DIMMs).

The notification system sends an alert to a system administrator when a DIMM exceeds a predefined

threshold for correctable memory errors. This lets the administrator schedule server maintenance to

replace a DIMM that may fail, avoiding unexpected interruption of business operations.

In the ProLiant System ROM upgrade (version May 2011 or later), we have enhanced protection with

HP Advanced Memory Error Detection Technology. This innovation seeks out specific defects that

either cause performance degradation or significantly increase the probability of an uncorrectable

(non-recoverable) memory condition. By improving the prediction of non-recoverable memory events,

this technology prevents unnecessary DIMM replacements and increases server uptime.

This paper details the enhancements in and advantages of HP Advanced Memory Error Detection

Technology. It begins with a description of Synchronous DRAM (SDRAM) technology and memory

errors, and it explains why memory errors are occurring more frequently.

SDRAM technology

A standard Error Correction Code (ECC) DDR3 DIMM delivers 72 bits at a time to a memory bus. The

72-bit data block—a 64-bit data word and 8 bits of ECC—is called a rank. As shown in Figure 1,

one rank consists of data from nine DRAM chips that provide 8 bits each (called x8 or “by 8” chips)

or 18 DRAM chips that provide 4 bits each (x4 chips). DIMMs are classified as single-rank, dual-rank,

or quad-rank (not shown). Quad-ranked DIMMs can have 72 x4 DRAM chips or 36 x8 DRAM chips,

including ECC chips. Memory manufacturers use multiple ranks to increase the capacity of DIMMs per

memory channel. Today, a quad-ranked DDR3 DIMM with 4 Gb DRAM chips has a usable capacity

of 32 GB.

Figure 1: Single-sided and double-sided SDRAM DIMMs and corresponding DIMM rank