UPduino Documentation Release 0.
Contents 1 tinyVision.ai 1.1 UPDuino v3.0: PCB Design Files, Designs, Documentation . . . . . . . . . . . . . . . . . . . . . .
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CHAPTER 1 tinyVision.ai 1.1 UPDuino v3.0: PCB Design Files, Designs, Documentation The UPDuino v3.0 is a small, low-cost FPGA board. The board features an on-board FPGA programmer, flash and LED with _all_ FPGA pins brought out to easy to use 0.1” header pins for fast prototyping. The tinyVision.ai UPduino v3.0 Board Features: • Lattice UltraPlus ICE40UP5K FPGA with 5.3K LUTs, 1Mb SPRAM, 120Kb DPRAM, 8 Multipliers • FTDI FT232H USB to SPI Device • _ALL_ 32 FPGA GPIO on 0.
UPduino Documentation, Release 0.1 • osresearch: large collection of very useful code and a good overview. • UPduino FPGA tutorial using APIO • A very detailed blog on implementing a RISCV in the FPGA • Digi-Key FPGA Playlist: “What is an FPGA” all the way to designing a risc-v custom peripheral in just 12 videos filled with great tutorials, links, and explanations. TinyVision.ai blog posts: • Magic Smoke and PTC’s • Lattice Modelsim on Windows • Ground trampolines and Phase Locked Loops 1.1.
UPduino Documentation, Release 0.1 Go there, open the apio folder, and replace its contents (but not the folder itself) with the contents of the “apio” folder in the downloaded commit of the apio directory. Note: If you would like to be able to easily update it, as apio is frequently updated due to its open sourse nature, you can use Git. Note, this process of replacement is limited to pip. If you use a different package manager, refer to where it stores its downloaded and installed packages.
UPduino Documentation, Release 0.1 • open fpga verilog tutorial. Tools • Icarus Verilog. • GTKWave. • Verilator. UPduino Examples • XarkLabs SystemVerilog Example - demonstrates simulation and other aspects of a more complete software toolchain 1.1.5 Specifications The UPduino supports the following features: • Lattice iCE40 UP5K UG48 FPGA UPduino Pinout The UPduino pinout was kindly provided by Xark below. • G0/G1/G3/G6 refer to Global clock inputs.
UPduino Documentation, Release 0.1 (continued from previous page) gpio_34 gpio_43 gpio_36 gpio_42 gpio_38 gpio_28 | 19 30 | | 20 29 | | 21 28 | | 22 27 | | 23 26 | | 24 25 | ------------------- gpio_3 gpio_48 gpio_45 gpio_47 gpio_46 gpio_2 1.1.6 Errata Please note that the silkscreen on the UPduino 3.0 has a bug. The GND and 12MHz clock pins are exchanged. (Pins 41 and 42 in the drawing above). The drawing above is correct and the silkscreen is wrong for these 2 pins. 1.1.
UPduino Documentation, Release 0.1 • Make it blink in a different interval • Make it go fast • How about slow? • Can the LED stay on a solid color? • Try different brightness values - How bright can it go? How many levels are there? - Can you do a “breathing” effect, where the LED eases in and out of brightness? There are endless possibilities with this board! Getting an LED to blink is just the start. . . 1.1.8 How to connect the two banks in the FPGA to a voltage other than 3.
UPduino Documentation, Release 0.1 Bank 0: Cut the trace for R31 (shorted on the board) and solder across R19. Bank 2: Cut the trace for R20 (shorted on the board) and solder across R26. 1.1.9 How to use the oscillator options on the UPduino? The UPduino has an on-board oscillator that generates 12MHz. This clock is generated by an oscillator and distributed to the FTDI, an external pin and also to a global buffer on the FPGA via an optional jumper.
UPduino Documentation, Release 0.1 The 12MHz can be routed to the FPGA directly on the board to preserve signal quality and also to minimize external connection by shorting R16. Note that this marked as OSC on the silkscreen for clarity. 1.1.10 How to program the FPGA CRAM? The FPGA on the UPduino can be programmed by either programming the flash and letting the FPGA reconfigure itself after a reset (default) or by programing the FPGA under direct control of the FTDI part (CRAM programming).
UPduino Documentation, Release 0.1 The default (flash) board layout is shown below: Removing R12/R13 and installing R11/R27 would look like the following layout: 1.1. UPDuino v3.
UPduino Documentation, Release 0.1 1.1.11 How to enable qSPI flash for _much_ higher flash throughput (up to 8x!) The UPduino flash is a qSPI/DTR capable device. ie. it is capable of operating with four IO’s instead of a single IO and also using both edges of the clock, effectively giving 8x the bandwidth on the SPI bus. In an actual use case, this bandwidth increase will only happen for burst read/writes.
UPduino Documentation, Release 0.1 1.1.12 How to enable the tinyFPGA bootloader support in the UPduino? 1.1.13 How to map a RISCV processor into the UPduino? 1.1.14 How to use the UPduino as an OpenOCD debugger? 1.1.15 How to connect a PMOD device to the UPduino? The UPduino pinout is setup specifically so that connecting to a 3.3V PMOD device is very easy. The pins in the following region of the UPduino are laid out per the PMOD specification allow you to interface directly to any single PMOD peripheral.
UPduino Documentation, Release 0.1 1.1.16 How to add a slave select to the FPGA from the FTDI 12 Chapter 1. tinyVision.
