User's Manual

Circuit Descriptions
3.3 Detailed Circuit Descriptions
3
3-19
and the time lapse between two different known threshold crossings is measured. Thus
dV, I and dt are known and the capacitance can be calculated.
The unknown capacitance Cx is connected to the red Input A safety banana socket, and
the black COM input. The T-ASIC supplies a constant current to Cx via relay contacts
K173, and protection PTC resistor R172. The voltage on Cx is supplied to two
comparators in the C-ASIC via the LF input. The threshold levels th
1
and th
2
of the
comparators are fixed (see Figure 3-9). The time lapse between the first and the second
threshold crossing depends on the value of Cx. The resulting pulse is supplied to the
TRIGGER output pin 29, which is connected to the analog trigger input of the T-ASIC
(TRIG-A signal). The T-ASIC adjusts the pulse to an appropriate level, and supplies it
to the D-ASIC via its ALLTRIG output. The pulse width is measured and processed by
the D-ASIC, and represented on the LCD as numerical reading. There will be no trace
displayed.
+Ire
f
-Iref
th1
th2
I-Cx
U-Cx
pos. clamp active
neg. clamp active neg. clamp active
0
0
ref clamp
TRIG-A
Figure 3-9. Capacitance Measurement
The T-ASIC supplies a positive (charge) and a negative (discharge) current. A
measurement cycle starts from a discharged situation (U
CX
=0) with a charge current.
After reaching the first threshold level (th
1
) the pulse width measurement is started. The
dead zone between start of charge and start of pulse width measurement avoids
measurement errors due to a series resistance of Cx.
The pulse width measurement is stopped after crossing the second threshold level (th
2
),
the completes the first part of the cycle.
Unlimited increase of the capacitor voltage is avoided by the positive clamp in the T-
ASIC. The output of the high impedance buffer in the C-ASIC supplies a replica of the
voltage across Cx to output pin 23 (ADDRESS). Via R165, this voltage is supplied to a
clamp circuit in the T-ASIC (SENSE, pin 59). This clamp circuit limits the positive
voltage on Cx to 0.45V.
Now the second part of the measurement is started by reversing the charge current. The
capacitor will be discharged in the same way as the charge cycle. The time between
passing both threshold levels is measured again. A clamp limits the minimum voltage on
Cx to 0V.
Averaging the results of both measurements cancels the effect of a possible parallel
resistance, and suppresses the influence of mains interference voltages.
Table 3-5 shows the relation between the capacitance ranges, the charge current and the
pulse width at full scale.