DDR4 Memory Technology

Technical white paper | DDR4 Memory Technology on HP Z Workstations

Registered DIMMs (RDIMMs) use registers to buer the command and address signals, as shown in the gure below.

The data bits are not buered. All RDIMMs support ECC as well as parity protection on the command and address

signals. RDIMMs should be used for higher reliability and for cost savings on higher capacities. Both x8 and x4 DRAMs

can be supported, allowing larger memory capacities than UDIMMs by essentially doubling the number of DRAM

chips which can be installed on a DIMM. RDIMMs can also present a large price advantage compared to large capacity

UDIMMs as new DRAM chip density carries a price premium over the current high volume DRAM density.

Load Reducing DIMMs (LR DIMMs) are a newer technology that use registers to buer command, address, and data

signals, as shown in the gure below. ECC and parity are supported on LR DIMMs. LR DIMMs were created to reduce

the electrical load on the system’s memory data bus to a single load. This buering architecture removes some

of the speed and signal integrity limitations experienced with RDIMMs, and enables added capacity at increased

speeds. The reduced load enables the use of quad and octal rank DIMM architecture. Octal rank DIMMs double the

memory capacity over a quad rank RDIMM. There are also power savings per Gigabyte and added clock latency when

compared to an RDIMM. Only x4 DRAMs are supported. LR DIMMs should be used if high capacity memory using

today’s technology is desired.