Operating instructions

12
MORSE is a CPU output that can be used to generate a CWID (Continuous Wave
Identification) code. This is a 1028Hz tone which is keyed on and off in a Morse code
as a staion identifier. (See 5.4)
The RESET pin is both a low active input and a low active output to the CPU. If
generated externally to the CPU, it forces the CPU into reset, and if the CPU executes a
RESET instruction,
this pin will be driven low by the CPU.
Whenever there is insufficient volts (< 4.65V) on pin 2 of the MC33064D (U203), it
will keep its RES output low. After the voltage has met the right level it will assert its
output low for another 200 milliseconds. Thus the CPU will be held in reset until VCC
is at the correct level. Thus the PWR_OK LED will only light when VCC is within
specification, and RESET has been released.
S200 is a momentary push-button switch that, when pressed, will cause the CPU to be
reset.
MOD_PLL_SEL is a serial bus select pin. It is used to select the Modulation PLL chip
(U602). (See 5.6)
LCD_DB7, LCD_RS, LCD_R/W, and LCD_E are reserved for interfacing to an LCD
display module. Note that this feature has not been implemented.
U205 is used to select whether the Flash or RAM is to be read or written.
U207 is a single supply, 5V, TSOP40 Flash chip of size 8, 16, or 32 Megabits, and is
used to store the firmware.
U208 is a 1, or 4, Megabit Static RAM in an SOP-32 package, and is used for both code
and data. The code in the RAM is copied from the Flash, at start-up.
5.3 Audio Processing Section (Sheet 3)
Sheet 3 is a schematic, which itself refers to two other sheets.
Sheet 3 shows how the two Line inputs go to audio transformers T300 and T301, are
then optionally terminated by analogue switches U301B, and U301C, before being
passed to the audio input stages described by Sheet 4.
It also shows how the Direct Audio (TONE) signal is passed to the Tone circuitry (sheet
5).
It also shows how dc current in Line1 will cause the
opto-isolator (U300) to generate
the CPU input LOOP_DET.
Relay RL300 is used to drive current back through an externally generated dc loop,
when the CPU output LOOP/VOLTS_SEL is high.
The output of the Tone circuitry and the Audio circuitry are mixed (summed) and
amplified by U302. It is then passed through a high order low pass filter (3.1kHz),
before being attenuated by digital POT U303.
U403D adds an extra 1.8% gain of the summed modulation signal. It effectively adds
another bit of control to the maximum deviation level.
The Digital POT (U303), in conjunction with U403D, set the Maximum deviation.
U302C then adds 6dB of gain before sending the audio to the modulator.
R317, D307, and C304, act as an average peak detector. This enables the CPU to
determine the size of signals being handled by the audio section.