Incor User's Guide Ethernet Media Access Controller TMS320C645x DSP

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5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)
EMAC Port Registers
The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in Figure 74 and
described in Table 74 .
Figure 74. Transmit Channel n DMA Head Descriptor Pointer Register (TX nHDP)
31 16
TX nHDP
R/W-x
15 0
TX nHDP
R/W-x
LEGEND: R/W = Read/Write; - n = value after reset
Table 74. Transmit Channel n DMA Head Descriptor Pointer Register (TX nHDP) Field Descriptions
Bit Field Value Description
31-0 TX nHDP Transmit channel n DMA Head Descriptor pointer. Writing a transmit DMA buffer descriptor address
to a head pointer location initiates transmit DMA operations in the queue for the selected channel.
Writing to these locations when they are nonzero is an error (except at reset). Host software must
initialize these locations to zero on reset.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)132 SPRU975B – August 2006
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