Stereo System User Manual

www.ti.com
2.7 Memory Map Summary
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
A high-level memory map of the C672x DSP appears in Table 2-8 . The base address of each region is
listed. Any address past the end address must not be read or written. The table also lists whether the
regions are word-addressable or byte- and word-addressable.
Table 2-8. C672x Memory Map
DESCRIPTION BASE ADDRESS END ADDRESS BYTE- OR WORD-ADDRESSABLE
Internal ROM Page 0 (256K Bytes) 0x0000 0000 0x0003 FFFF Byte and Word
Internal ROM Page 1 (128K Bytes) 0x0004 0000 0x0005 FFFF Byte and Word
Internal RAM Page 0 (256K Bytes) 0x1000 0000 0x1003 FFFF Byte and Word
Memory and Cache Control Registers 0x2000 0000 0x2000 001F Word Only
Emulation Control Registers (Do Not Access) 0x3000 0000 0x3FFF FFFF Word Only
Device Configuration Registers 0x4000 0000 0x4000 0083 Word Only
PLL Control Registers 0x4100 0000 0x4100 015F Word Only
Real-time Interrupt (RTI) Control Registers 0x4200 0000 0x4200 00A3 Word Only
Universal Host-Port Interface (UHPI) Registers 0x4300 0000 0x4300 0043 Word Only
McASP0 Control Registers 0x4400 0000 0x4400 02BF Word Only
McASP1 Control Registers 0x4500 0000 0x4500 02BF Word Only
McASP2 Control Registers 0x4600 0000 0x4600 02BF Word Only
SPI0 Control Registers 0x4700 0000 0x4700 007F Word Only
SPI1 Control Registers 0x4800 0000 0x4800 007F Word Only
I2C0 Control Registers 0x4900 0000 0x4900 007F Word Only
I2C1 Control Registers 0x4A00 0000 0x4A00 007F Word Only
McASP0 DMA Port (any address in this range) 0x5400 0000 0x54FF FFFF Word Only
McASP1 DMA Port (any address in this range) 0x5500 0000 0x55FF FFFF Word Only
McASP2 DMA Port (any address in this range) 0x5600 0000 0x56FF FFFF Word Only
dMAX Control Registers 0x6000 0000 0x6000 008F Word Only
MAX0 (HiMAX) Event Entry Table 0x6100 8000 0x6100 807F Byte and Word
Reserved 0x6100 8080 0x6100 809F
MAX0 (HiMAX) Transfer Entry Table 0x6100 80A0 0x6100 81FF Byte and Word
MAX1 (LoMAX) Event Entry Table 0x6200 8000 0x6200 807F Byte and Word
Reserved 0x6200 8080 0x6200 809F
MAX1 (LoMAX) Transfer Entry Table 0x6200 80A0 0x6200 81FF Byte and Word
External SDRAM space on EMIF 0x8000 0000 0x8FFF FFFF Byte and Word
External Asynchronous / Flash space on EMIF 0x9000 0000 0x9FFF FFFF Byte and Word
EMIF Control Registers 0xF000 0000 0xF000 00BF Word Only
(1)
(1) The upper byte of the EMIF’s SDRAM Configuration Register (SDCR[31:24]) is byte-addressable to support placing the EMIF into the
Self-Refresh State without triggering the SDRAM Initialization Sequence.
Submit Documentation Feedback Device Overview 15