Data Sheet

13
TCA9548A
www.ti.com SCPS207F –MAY 2012–REVISED NOVEMBER 2016
Product Folder Links: TCA9548A
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8.3 Feature Description
The TCA9548A is an 8-channel, bidirectional translating switch for I
2
C buses that supports Standard-Mode (100
kHz) and Fast-Mode (400 kHz) operation. The TCA9548A features I
2
C control using a single 8-bit control register
in which each bit controls the enabling and disabling of one of the corresponding 8 switch channels for I
2
C data
flow. Depending on the application, voltage translation of the I
2
C bus can also be achieved using the TCA9548A
to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication
on the I
2
C bus enters a fault state, the TCA9548A can be reset to resume normal operation using the RESET pin
feature or by a power-on reset which results from cycling power to the device.
8.4 Device Functional Modes
8.4.1 RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal
is asserted low for a minimum of t
WL
, the TCA9548A resets its registers and I
2
C state machine and deselects all
channels. The RESET input must be connected to V
CC
through a pull-up resistor.
8.4.2 Power-On Reset
When power is applied to the VCC pin, an internal power-on reset holds the TCA9548A in a reset condition until
V
CC
has reached V
PORR
. At this point, the reset condition is released, and the TCA9548A registers and I
2
C state
machine are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter,
V
CC
must be lowered below V
PORF
to reset the device.
8.5 Programming
8.5.1 I
2
C Interface
The TCA9548A has a standard bidirectional I
2
C interface that is controlled by a master device in order to be
configured or read the status of this device. Each slave on the I
2
C bus has a specific device address to
differentiate between other slave devices that are on the same I
2
C bus. Many slave devices require configuration
upon startup to set the behavior of the device. This is typically done when the master accesses internal register
maps of the slave, which have unique register addresses. A device can have one or multiple registers where
data is stored, written, or read.
The physical I
2
C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to V
CC
through a pull-up resistor. The size of the pull-up resistor is determined by the amount
of capacitance on the I
2
C lines. (For further details, see the I
2
C Pull-up Resistor Calculation application report.
Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are
high after a STOP condition (See Figure 7 and Figure 8).
The following is the general procedure for a master to access a slave device:
1. If a master wants to send data to a slave:
– Master-transmitter sends a START condition and addresses the slave-receiver.
– Master-transmitter sends data to slave-receiver.
– Master-transmitter terminates the transfer with a STOP condition.
2. If a master wants to receive or read data from a slave:
– Master-receiver sends a START condition and addresses the slave-transmitter.
– Master-receiver sends the requested register to read to slave-transmitter.
– Master-receiver receives data from the slave-transmitter.