User manual

10.1 Reset Overview
10.2 Reset Pins
Reset Overview www.ti.com
There are six types of reset in the TMS320DM646x DMSoC. The types of reset differ by how they are
initiated and/or by their effect on the device. Each type is briefly described in Table 10-1 and further
described in the following sections.
Table 10-1. Reset Types
Type Initiator Effect
Power-on reset (POR) POR pin active low Total reset of the chip (cold reset). Resets all modules including
memory and emulation. Total reset of chip (cold reset). Activates
the POR signal on-chip, which resets the entire chip including
the emulation logic. POR assertion also causes internal TRST
signal to be asserted. The power-on reset ( POR) must be driven
low during power-ramp of the device. Device boot and
configuration pins are latched.
Warm reset RESET pin active low Resets all modules including memory, except emulation logic.
Deassertion of RESET causes latching of the device boot and
configuration pins. Emulator stays alive during Warm reset.
Maximum (Max) reset Emulator or Watchdog Timer Same as Warm reset, except the device boot and configuration
(Timer2) pins are not relatched.
System reset Emulator A soft reset. A soft reset maintains memory contents, and does
not affect or reset clocks or power states. Does not reset
emulation logic, nor relatch device boot and configuration pins.
Module reset Software Resets a specific module. Allows the software to independently
reset any module.
DSP local reset ARM software Resets the DSP CPU. The DSP internal memories (L1P, L1D,
and L2) are not reset. Allows the ARM to reset and boot the
DSP.
Test reset (TRST) TRST pin Test reset on JTAG interface. Drive TRST pin low to reset the
test and emulation logic ( POR is also ANDed with the reset from
this pin before going to the test reset targets). For proper DSP
operation, TRST should always be 0 (active low) during normal
functional mode of operation. Also, the TRST pin is required to
be pulled high externally for proper ARM emulaton operation.
Power-on reset, Warm reset, and Test reset are initiated by the POR, RESET, and TRST pins,
respectively. These pins are briefly described in Table 10-2 . For more information, see the device-specific
data manual.
Table 10-2. Reset Pins
Pin Name Type Description
POR Input Power-on reset
RESET Input Active-low device reset
TRST Input JTAG test-port reset
Reset112 SPRUEP9A – May 2008
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