User manual

10.3.7 Test and Emulation Reset ( TRST pin)
10.4 Default Device Configurations
10.4.1 Device Configuration Pins
www.ti.com Default Device Configurations
This is the Test reset on JTAG interface. Drive the TRST pin low to keep the test and emulation logic in
reset. TRST needs to be released (pulled high) whenever it is necessary to use a JTAG controller to
debug the device. You can pull the TRST pin high on the board if emulation is required.
After POR, Warm reset, and Max reset, the chip is in its default configuration. This section highlights the
default configurations associated with PLLs, clocks, ARM boot mode, EMIFA, and DSP boot mode.
Note: Default configuration is the configuration before the boot process begins. The boot ROM
updates the configuration. See Chapter 11 for more information on the boot process.
The device configuration pins are latched at the end of power-on reset or Warm reset.
The boot configuration register (BOOTCFG) in the System Module is a read-only register that indicates
the value of the device configuration pins latched at the end of reset. During a hard reset ( POR or RESET
pin active [low]), the values of the device configuration pins (BTMODE[3:0], CS2BW, PCIEN, and
DSPBOOT) are propagated through BOOTCFG to the Boot Controller. When RESET or POR is
deasserted (raising edge), the value of the pins is latched. The BOOTCFG value does not change as a
result of a soft reset, instead the value latched at the end of the previous global reset is retained.
BOOTCFG is shown in Figure 10-1 and described in Table 10-3 . See device-specific data manual for
details on BOOTCFG.
The device configuration pins allow you to configure the following options at reset:
• Boot Mode (BTMODE[3:0] pins)
• EMIFA EM_CS2 default bus width (CS2BW pin)
• PCI enable (PCIEN pin)
• DSP Boot Mode (DSPBOOT pin)
Note: The device configuration pins are multiplexed with pins of the video port interface (VPIF).
After the device configuration pins are latched at reset, they automatically change to function
as VPIF pins. Pin multiplexing is described in Chapter 9 .
Figure 10-1. Boot Configuration Register (BOOTCFG)
31 18 17 16
Reserved DSP_BT PCIEN
R-0 R-L R-L
15 9 8 7 4 3 0
Reserved CS2_BW Reserved BOOTMODE
R-0 R-L R-0 R-L
LEGEND: R = Read only; L = Latched pin value; - n = value after reset
SPRUEP9A – May 2008 Reset 115
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