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2.10 Flow Control
2.11 Reset Considerations
2.11.1 Software Reset Considerations
2.11.2 Hardware Reset Considerations
2.12 Interrupt Support
2.12.1 Interrupt Events and Requests
Peripheral Architecture
The VLYNQ module includes flow control features. The VLYNQ module automatically generates flow
control enable requests, /P/, when the RX/inbound FIFOs (FIFO1 and FIFO2) resources are consumed.
The FIFOs can take up to 16 32-bit words.
The remote device will begin transmitting idles, /I/, starting on the first byte boundary following reception of
the request. When sufficient RX FIFO resources have been made available, a flow control disable request,
/C/, is transmitted to the remote device. In response, the remote device will resume transmission of data.
See Appendix A .
Peripheral clock and reset control is done through the power and sleep controller (PSC) module that is
included with the device. For more information, refer to the power management section (Section 2.14 ).
Additionally, there is a software reset (the reset bit in the VLYNQ control register, CTRL) within the
peripheral itself. Writing a 1 to the reset bit resets all of the internal state machines of the VLYNQ module,
the serial interface is disabled, and the link is lost. The VLYNQ module remains in reset until the software
clears the bit.
Note: When setting the reset bit, the VLYNQ status register (STAT) value is the only value that is
set to the default value. All of the other VLYNQ memory-mapped registers retain their values
prior to the software reset.
When a hardware reset occurs, the VLYNQ peripheral resets its register values to the default values and
the serial interface is disabled. After a hardware reset, the VLYNQ memory mapped registers and any
chip-level registers that are associated with VLYNQ (for example, pin multiplexing registers) must be
configured appropriately before data transmission can resume.
Note: Be cautious when only resetting one of the VLYNQ devices after two or more VLYNQ
devices have established a link. If only one of the VLYNQ devices is in reset, then no data
activity can occur across the serial interface during the time of reset.
The VLYNQ module interrupt VLQINT is mapped to the GEMINTC.
Interrupts generate when bits are set in the VLYNQ interrupt pending/set register (INTPENDSET). Bits are
set in the INTPENDSET register when any of the following occur:
• Writing directly to the INTPENDSET
• Remote interrupt (via the serial interrupt packet)
• Serial bus error
When the VLYNQ interrupt pending/set register (INTPENDSET) is a non-zero value, the method of
forwarding the interrupt status depends on the state of the INTLOCAL bit in the VLYNQ control register
(CTRL).
• When INTLOCAL = 0, the contents of INTPENDSET are inserted into an interrupt packet and sent
over the serial interface. When packet transmission completes, the associated bits clear in
INTPENDSET.
SPRUF89 – October 2007 VLYNQ Port 21
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