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efficiency. The internal memory architecture in the C621x/C671x/C64x DSPs is organized in a
two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache
(L1D) on the first level. Accesses by the CPU to the these first level caches can complete without
CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from
the next lower memory level, L2 or external memory.
SPRU862 — TMS320C64x+ DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the TMS320C64x+
digital signal processor (DSP) of the TMS320C6000 DSP family can be efficiently used in DSP
applications. Shows how to maintain coherence with external memory, how to use DMA to reduce
memory latencies, and how to optimize your code to improve cache efficiency. The internal memory
architecture in the C64x+ DSP is organized in a two-level hierarchy consisting of a dedicated
program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to
the these first level caches can complete without CPU pipeline stalls. If the data requested by the
CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external
memory.
Read This First12 SPRUEP9A – May 2008
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