User manual

12.1 Introduction
12.2 Shared Peripherals
Introduction www.ti.com
The TMS320DM646x DMSoC integrates an ARM core for overall system control functions and a DSP
subsystem for complex data and image/video processing functions. Figure 12-1 shows the
interconnections between the ARM and the DSP cores and the shared resources. Both the ARM and the
DSP have access to the EDMA, McASP, Timer0, and Timer1 peripherals. Both the ARM and DSP have
access to several blocks of shared memory, including ARM internal memory, DSP internal memory, and
external memory of the DDR2 memory controller and asynchronous EMIF (EMIF). The system control
module includes registers that allow the ARM to interrupt the DSP and conversely allow the DSP to
interrupt the ARM. The power and sleep controller (PSC) and the system control module (SYS) provide
the ARM with a set of registers to boot the DSP, enable/disable the DSP clock, and reset the DSP.
In summary, ARM-DSP integration includes all of the following features:
• Shared peripherals
– ARM and DSP have access to EDMA
– ARM and DSP have access to McASP
– ARM and DSP have access to Timer0 and Timer1
• Shared memory
– ARM has access to DSP internal memory (L1P, L1D, L2)
– DSP has access to ARM internal memory
– ARM and DSP have access to DDR2 memory controller and asynchronous EMIF
• ARM-DSP interrupts
– ARM can interrupt the DSP (via 4 general interrupts and 1 NMI)
– DSP can interrupt the ARM (via 1 general interrupt)
• ARM control of DSP clock, reset, and boot
– ARM can boot the DSP
– ARM can control the DSP
– Clock on/off
– ARM can assert/deassert DSP module and local resets
These features are described in the following sections.
The following peripherals are fully accessible by both the ARM and the DSP.
• EDMA
• McASP
• Timer0 and Timer1
Both the ARM and the DSP access these peripherals through the configuration bus. See Chapter 4 for
information on the configuration bus.
124 ARM-DSP Integration SPRUEP9A – May 2008
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