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12.4 ARM-DSP Interrupts
www.ti.com ARM-DSP Interrupts
The ARM can interrupt the DSP; conversely, the DSP can interrupt the ARM. These interrupts are
generally used to allow the ARM and the DSP to coordinate. For example, the ARM may interrupt the
DSP when it is ready to have the DSP process some data buffer in shared memory. A typical sequence is
as follows:
• ARM writes command in shared memory
• ARM interrupts DSP
• DSP responds to interrupt and reads command in shared memory
• DSP executes a task based on the command
• DSP interrupts ARM upon completion of the task
This sequence is often referred to as ARM-DSP communication.
The ARM has access to five DSP interrupt events, ARM2DSP0, ARM2DSP1, ARM2DSP2, ARM2DSP3,
and NMI, in the DSP interrupt event map. The DSP has access to one ARM interrupt event, DSP2ARM0,
in the ARM interrupt event map. The ARM-DSP interrupts/events are summarized in Table 12-1 .
Table 12-1. ARM-DSP Interrupt Mapping
Source Interrupt Number
Name Description ARM DSP AINTC INTC
DSP2ARM0 DSP Controller to ARM Interrupt - x 45 -
ARM2DSP0 ARM to DSP Controller 0 Interrupt x - - 16
ARM2DSP1 ARM to DSP Controller 1 Interrupt x - - 17
ARM2DSP2 ARM to DSP Controller 2 Interrupt x - - 18
ARM2DSP3 ARM to DSP Controller 3 Interrupt x - - 19
NMI Nonmaskable Interrupt x - - -
The System Module includes registers for generating interrupts from the ARM to the DSP (DSPINT,
DSPINTSET, and DSPINTCLR) and from the DSP to the ARM (DSPINT, DSPINTSET, and DSPINTCLR).
See the device-specific data manual for details on these registers.
The ARM uses DSPINT, DSPINTSET, and DSPINTCLR to generate an interrupt to the DSP. The DSP
interrupt status register (DSPINT) shows the status of the ARM-to-DSP interrupts. The ARM may generate
an interrupt to the DSP by setting one of the four INTDSP n bits or the INTNMI bit in the DSP interrupt set
register (DSPINTSET). The interrupt set (INTDSP n) bit then self-clears and the corresponding bit in
DSPINT is automatically set to indicate that the interrupt was generated. After servicing the interrupt, the
DSP clears the status bit in DSPINT by writing a 1 to the corresponding bit in the DSP interrupt clear
register (DSPINTCLR). The ARM may poll the status bit in DSPINT to determine when the DSP has
completed the interrupt service.
The DSP may generate an interrupt to the ARM in a similar manner using the ARM interrupt set register
(ARMINTSET) and the ARM interrupt clear register (ARMINTCLR). The DSP can monitor the status of the
DSP-to-ARM interrupts using the ARM interrupt status register (ARMINT).
For more information on ARM interrupts, see Chapter 8 . For more information on DSP interrupts, see the
DSP interrupts section of the TMS320DM646x DMSoC DSP Subsystem Reference Guide (SPRUEP8 ).
For more information on the system control module, see Chapter 9 .
SPRUEP9A – May 2008 ARM-DSP Integration 127
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