User's Guide

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Timer Operation

3.5 Timer Counting

The timer counter runs at the timer clock rate specified by the clock source bit (CLKSRC) in the timer

control register (TCR). Counting is enabled by setting the enabling mode (ENAMODE) bits in TCR to 01b

or 10b. When enabled, the timer counter starts incrementing until the counter reaches a value equal to the

value in the timer period register. Once the timer counter matches the timer period:

• If the timer is set to enable one time (ENAMODE = 01b), the timer counter is reset to 0, then stops.

• If the timer is set to enable continuously (ENAMODE = 10b), the timer counter is reset to 0, then

continues counting.

Once the timer stops, if an external clock is used as the timer clock, the disable period must last at least

one external clock period or the timer will not start counting again. When using the external clock, the

count value is synchronized to the internal clock.

Note that when both the timer counter and timer period are cleared to 0, the timer can be enabled but the

timer counter does not increment because the timer period is 0.

3.6 Timer Reset Sources

The timer has two reset sources: hardware reset and the timer reset bits (TIMLORS and TIMHIRS) in the

timer global control register (TGCR).

• When a hardware reset is asserted, all the registers are set to their default values.

• When TIMLORS is cleared to 0, TSTAT_LO in TCR is reset to 0 and TOUTL is in the high-impedance

state.

• When TIMHIRS is cleared to 0, TSTAT_HI in TCR is reset to 0.

3.7 Timer Interrupt Rate

To receive periodic interrupts, configure the timer to run in the continuous mode (ENAMODE = 10b). Each

time the timer finishes counting, it can generate a timer interrupt for the CPU and a timer event for the

EDMA controller. The rate at which this occurs (the timer interrupt rate) depends on whether the timer has

a prescaler.

If the timer does not have a prescaler, there is only one counter. When the timer counter reaches the

programmed timer period, the timer generates an interrupt and an EDMA event. Because the timer is in

the continuous mode, one cycle after the timer counter matches the timer period, the timer counter is reset

to 0 and starts counting again. The timer interrupt rate is:

If a timer has prescaler, there are two counters. One cycle after the prescale counter reaches the

programmed prescale period, the timer counter is incremented by 1, and the prescale counter is reset to

start counting again. If the prescaler continues long enough, it increments the timer counter to the

programmed timer period. At that time, the timer generates an interrupt and an EDMA event. One cycle

later (assuming the continuous mode), the timer counter is reset to 0 and starts counting again. The timer

interrupt rate in this case is:

SPRU818B–December 2005–Revised September 2010 C6472/TCI648x 64-Bit Timer

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