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Watchdog Timer Mode

4 Watchdog Timer Mode

The timer can also be configured as a 64-bit watchdog timer. As a watchdog timer, it can be used to

prevent system lockup when the software becomes trapped in loops with no controlled exit. After a

hardware reset, the timer is configured as a 64-bit GP timer and the watchdog mode is disabled. The timer

then can be reconfigured as a watchdog timer using the timer mode (TIMMODE) bits in the timer global

control register (TGCR) and the watchdog timer enable (WDEN) bit in the watchdog timer control register

(WDTCR). In the watchdog timer mode, the timer requires a special service sequence to be executed

periodically. Without this periodic servicing, the timer counter increments until it matches the timer period

and causes a watchdog timeout event.

Once the timer is configured as a watchdog timer, it cannot be reconfigured as a GP timer until a device

reset occurs. When the timer counter matches the timer period, the timer generates two signals: an output

signal and an interrupt signal (described in Section 4.1). Typically, one or the other is used, depending on

whether an external or internal trigger is desired.

4.1 Timer Output Signal and Timer Interrupt Signal in Watchdog Mode

When the periodic service sequence is not met, the timer counter increments until it matches the period

and times out. During a time out, a pulse will be asserted on the timer output pin, and an internal

maskable interrupt (TINTLO) will be triggered. The timer output pin can be externally connected to the

non-maskable interrupt (NMI) pin of the device. Note that the timer pulse width must be configured to

generate an active low pulse long enough for the CPU to recognize it as a NMI pulse. The pulse width is

configured using the PWID bits of the timer control register (TCR).

4.2 Watchdog Timer Mode Restrictions

The watchdog timer mode is selected and enabled when TIMMODE = 10b in TGCR and WDEN = 1 in

WDTCR. This mode has the following restrictions:

• No dual 32-bit timers mode

• No gated clock

• No external clock

• No one-time enabling

• No clock mode (only pulse mode).

4.3 Watchdog Timer Mode Operation

Figure 11 shows the timer when it is used in the watchdog timer mode. Note that in this mode, the timer

clock must be set to the internal clock (CLKSRC_LO = 0). The CP_LO bit is forced to 0 because the pulse

mode is required for the watchdog timer operation. The counter registers (CNTLO and CNTHI) form a

64-bit timer counter register and the period registers (PRDLO and PRDHI) form a 64-bit period register.

When the timer counter matches the timer period, the timer generates a watchdog timeout event. This

event:

• Drives the timer output signal (TOUTL) and/or the timer interrupt signal (TINTLO).

• Resets the timer counter to 0.

• Sets the TSTAT_LO bit, which is copied to the WDFLAG bit of WDTCR.

The timer output signal can be connected externally to the NMI pin to generate a non-maskable interrupt,

if so desired.

SPRU818B–December 2005–Revised September 2010 C6472/TCI648x 64-Bit Timer

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