User's Guide

Initialstate
(watchdogmode
disabled)
(CNTHI/LO=x)
(PRDHI/LO=x)
Otherthan A5C6h
toWDKEY
TIMMODE=10b
TIMLORS=1
TIMHIRS=1
Power-up/Reset
(hardware/software)
Pre-active
state
WDEN=1;
A5C6hto
WDKEY
WDKEY
A5C6hto
DA7Ehto
WDKEY
(countercleared,
WDFLAGcleared)
OtherthanDA7Eh
or A5C6hto
WDKEY
Timeout
state
(watchdogmode
disabled)
Activestate
(waitingfor
A5C6h)
Otherthan A5C6h
orDA7EhtoWDKEY
(WDFLAGset,
TINTLOtriggered)
Timeout
(WDFLAGset,
TINTLOtriggered)
Service
state
(counter
countsup)
(waitingfor
DA7Eh)
A5C6htoWDKEY
DA7Ehto
WDKEY
(counter
cleared)
Timeout
(WDFLAGset,
TINTLOtriggered)
OtherthanDA7Eh
or A5C6htoWDKEY
(WDFLAGset,
TINTLOtriggered)
A5C6hto
WDKEY
Disabled
state
www.ti.com Watchdog Timer Mode
Figure 12. Watchdog Timer Operation State Diagram
Once the watchdog timer is activated, it can be disabled only by a watchdog timeout event or by a
hardware reset. A special key sequence is required to prevent the watchdog timer from being accidentally
serviced while the software is trapped in a dead loop or by some other software failure.
To prevent a watchdog timeout event, the timer has to be serviced periodically (you could use another
on-chip timer or an off-chip timer) by writing A5C6h followed by DA7Eh to the watchdog timer service key
(WDKEY) bits of WDTCR before the timer finishes counting up. Both A5C6h and DA7Eh are allowed to be
written to the WDKEY bits, but only the correct sequence of A5C6h followed by DA7Eh to the WDKEY bits
services the watchdog timer. Any other writes to the WDKEY bits triggers the watchdog timeout event
immediately. Writes to other bits in the WDTCR are ignored when the watchdog timer is active (see
Section 4.4).
When the watchdog timer is in the timeout state, the watchdog timer is disabled, the WDEN bit is cleared
to 0, and the timer is reset. After entering the timeout state, the watchdog timer cannot be enabled again
until a hardware reset occurs.
After a hardware reset, the watchdog timer is disabled; however, reads or writes to the watchdog timer
registers are allowed. Once the WDEN bit is set and A5C6h is written to the WDKEY bits, the watchdog
timer enters the pre-active state. In the pre-active state:
• A write to WDTCR is allowed only when the write comes with the correct key (A5C6h or DA7Eh) to the
WDKEY bits.
• A write of DA7Eh to the WDKEY bits when the WDEN bit is set to 1 resets the counters and activates
the watchdog timer.
21
SPRU818B–December 2005–Revised September 2010 C6472/TCI648x 64-Bit Timer
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