User's Guide

www.ti.com Timer Registers
5.4 Timer Control Register (TCR)
The timer control register (TCR) is shown in Figure 18 and described in Table 12. The lower 16 bits of
TCR determine the operating mode and monitor the status of TIMLO, as well as control the function of
TINPL and TOUTL. The upper 16 bits determine the operating mode and monitor the status of TIMHI. The
upper 16 bits of TCR are used only when the timer is configured in dual 32-bit timers unchained mode
(TIMMODE = 01b in TGCR).
Figure 18. Timer Control Register (TCR)
31 26 25 24
Reserved TIEN_HI
(A)
CLKSRC_HI
(A)
R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
ENAMODE_HI PWID_HI CP_HI Reserved INVOUTP_HI TSTAT_HI
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
15 10 9 8
Reserved TIEN_LO CLKSRC_LO
R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
ENAMODE_LO PWID_LO CP_LO INVINP_LO INVOUTP_LO TSTAT_LO
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
A. Bits 25 and 24 are available on the C6472/TCI6486 devices only; these bits are Reserved for TCI6482, TCI6484, and TCI6487/88
devices.
Table 12. Timer Control Register (TCR) Field Descriptions
Bit Field Value Description
31-26 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
25-24 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
(TCI6482,
TCI6484,
TCI6487/88)
25 TIEN_HI Timer input enable bit determines if the timer clock is gated by the timer input. Applicable only when
(C6472/TCI6486) CLKSRC_HI = 0.
0 Timer clock is not gated by the timer input.
1 Timer clock is gated by a high state of the timer input synchronized with the internal clock. Timer
starts counting when timer input transitions from low to high. Timer stops counting when timer input
transitions from high to low.
24 CLKSRC_HI Clock source bit determines the clock source for the timer.
(C6472/TCI6486)
0 The clock source is the internal clock.
1 The clock source is the signal on the timer pin.
23-22 ENAMODE_ HI Enabling mode bits determine the timer mode for TIMHI.
00b The timer is disabled (not counting) and maintains the current value.
01b The timer is enabled one time. The timer stops after the timer counter reaches the timer period.
10b The timer is enabled continuously. The timer counter increments until it reaches the timer period.
One timer clock cycle later, the timer counter is reset to 0 and continues counting.
11b Reserved
21-20 PWID_HI Pulse width bits for TIMHI. PWID_HI is only used in pulse mode (CP_HI = 0). PWID_HI controls the
width of the timer output signal. The polarity of the pulse is controlled by the INVOUTP_HI bit. The
timer output signal is recorded in the TSTAT_HI bit and can be made visible on the timer output pin.
00b The pulse width is 1 timer clock cycle.
01b The pulse width is 2 timer clock cycles.
10b The pulse width is 3 timer clock cycles.
11b The pulse width is 4 timer clock cycles.
27
SPRU818B–December 2005–Revised September 2010 C6472/TCI648x 64-Bit Timer
Submit Documentation Feedback
Copyright © 2005–2010, Texas Instruments Incorporated