User's Guide

Timer Registers

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5.1 Emulation Management and Clock Speed Register (EMUMGT_CLKSPD)

The EMUMGT_CLKSPD register contains the FREE and SOFT bits that determine how the timer

responds to an emulation suspend event (see Figure 13 and Table 9). An emulation suspend event

corresponds to any type of emulator access to the DSP, such as a hardware or software breakpoint, a

probepoint, or a printf instruction. For additional emulation information, see Section 3.8.

The CLKDIV field of this register can also be read to identify the ratio of the CPU clock to the timer input

clock. For example, in devices where the internal timer clock frequency is equal to the CPU frequency

divided by 6, the CLKDIV field will read as 6 on those devices.

Figure 13. Emulation Management and Clock Speed Register (EMUMGT_CLKSPD)

31 20 19 16

Reserved CLKDIV

R/W-0 R-n

(A)

15 2 1 0

Reserved SOFT FREE

R/W-0 R-0 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

A. The reset value of this field is based on the ratio of the CPU clock to the timer internal clock. To determine what this ratio is for your

device, see the device-specific data manual.

Table 9. Emulation Management and Clock Speed Register (EMUMGT_CLKSPD) Field Descriptions

Bit Field Value Description

31-20 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

19-16 CLKDIV Clock divide-down ratio bits. Defines the ratio of the CPU clock to the timer input clock. The

CLKDIV bits are read-only bits.

1h Internal clock source for the timer is the CPU clock divided by 1.

2h Internal clock source for the timer is the CPU clock divided by 2.

3h Reserved

4h Internal clock source for the timer is the CPU clock divided by 4.

5h Reserved

6h Internal clock source for the timer is the CPU clock divided by 6.

7h Reserved

8h Internal clock source for the timer is the CPU clock divided by 8.

9-15h Reserved

15-2 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

1 SOFT Used in conjunction with FREE bit to determine how the timer responds to an emulation suspend

event. When the FREE bit is 0, the SOFT bit selects the timer response.

0 The timer stops immediately.

1 The timer stops when the timer counter register increments and reaches the value in the timer

period register.

0 FREE Used in conjunction with SOFT bit to determine how the timer responds to an emulation suspend

event. When the FREE bit is 0, the SOFT bit selects the timer response.

0 The SOFT bit selects the timer response.

1 The timer runs free, regardless of the value of the SOFT bit.

C6472/TCI648x 64-Bit Timer SPRU818B–December 2005–Revised September 2010

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